MB86612 Ver la hoja de datos (PDF) - Fujitsu

Número de pieza

componentes Descripción

Lista de partido

MB86612

IEEE 1394 Bus Controller

Fujitsu 

MB86612

(2) End Receiving Operation

Parameter

ICLK rise to ILWRE rise

ILWRE rise to IV rise

Final data output disable time

ILWRE negate time*1

Symbol

tCHLH

tLHVH

tVHIDX

tLWH

Value

Min.

—

1 ticlk + 10

—

2 ticlk – 10

Max.

40

—

20

—

Unit

ns

ns

ns

ns

ICLK

IDIR

ILWRE

IERR* 2

TS* 2

IV

ID7 to ID0

tCHLH

tLWH

N-2

tLHVH

N-1

tVHIDX

N

Hi − Z

*1: The MB86612 operates in ‘negate mode’, in which the ILWRE signal is negated for each source packet received,

as well as ‘assert mode’, in which the ILWRE signal is continuously asserted as long as ISO sending and

receiving FIFO writing are enabled. The above timing chart shows operation in negate mode. If there one or

more packets of empty space are present in the sending or receiving FIFO area, the ILWRE signal is again

asserted.Note that even in assert mode, if writing to the ISO sending or receiving FIFO areas is disabled, the

ILWRE signal is negated according to the timing shown above, and re-asserted when writing is again enabled.

*2: The TS (in MPEG mode) and IERR signals are negated in synchronization with the ILWRE signal.

32

Share Link: