MB86612 Ver la hoja de datos (PDF) - Fujitsu

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MB86612

IEEE 1394 Bus Controller

Fujitsu 

MB86612

s INTERNAL REGISTERS

The MB86612 internal registers have 3-bank construction, with 16-bit access to all registers.

Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary

for AV/C (MPEG, DVC) operation, and bank 2 contains CSR’s.

In addition each bank has registers used in common for MB86612 device control.

1. Bank Common Registers

The following registers can be accessed in any bank from bank 0 to bank 2.

Address

HEX A5 A4 A3 A2 A1

Write operation

Read operation

00 0 0 0 0 0

mode-control register

←

02 0 0 0 0 1

(reserved)

flag & status register

04 0 0 0 1 0

instruction fetch register

←

06 0 0 0 1 1

interrupt mask register

interrupt code register

08 0 0 1 0 0

(reserved)

Receiving acknowledge display

register

0A 0 0 1 0 1

ASYNC data port (sending)

ASYNC data port (receiving)

0C 0 0 1 1 0

(reserved)

←

0E 0 0 1 1 1

(reserved)

←

3E 1 1 1 1 1

bank select register

←

34

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