MB86613S Ver la hoja de datos (PDF) - Fujitsu
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MB86613S Datasheet PDF : 134 Pages
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Preliminary
Bit
----
31:24
23:16
15:8
Field Name
--------------
base_class
sub_class
prog_if
rwcu
----
r
r
r
reset
--------
0Ch
00h
10h
description
------------------------------------------
These bits indicate ”0Ch” for the serial bus controller.
These bits indicate ”00h” for the IEEE1394 compliant.
These bits indicate ”10h” for the Open HCI.
3.1.7. Cache Line Size
This register specifies the cache line size in 32- bit long- word that is guaranteed for the memory write and
invalidate command.
7
0
line_size
Bit
----
7:0
Field Name
rwcu
-------------- ----
line_size
rw
reset
--------
00h
description
--------------------------------------------
These bits specify the cache line size with the following
setting:
Value Size
----- -----------------------------------
00h Unused for memory write & invalidate command
01h - 1- to 255- long word.
FFh
3.1.8. Latency Timer
This register specifies the PCI latency timer value. The latency timer counts the time from the FRAME# as-
serted until the PCI bus occupied.
15
8
latency_clks
Bit
Field Name
rwcu
---- -------------- ----
15:11 latency_clks
rw
reset
--------
00h
description
------------------------------------------
These bits specify the latency timer. The unit is 8 PCI
clocks.
3.1.9. Header Type
This register indicates the register configuration at addresses 10h to 3Fh in configuration space and the sup-
ported function(s). MB86613S supports the single- function so this register indicates ”00h”.
23
16
header_type
17
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