MX98704EC Ver la hoja de datos (PDF) - Macronix International
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MX98704EC Datasheet PDF : 15 Pages
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5.0 FUNCTIONAL DESCRIPTION
Functional block diagram of the complete chip.
TDAT4-0
SYMCLK
XTAL1,
XTAL2
TCLKIN
RDAT4-0
Input
Register
Shifter
NRZ/
NRZI
25 Mhz
Crystal
Oscillator
Output
Register
Clock Multiplier (PLL)
NRZ/
NRZI
Shifter
Output
Control
Media
Interface
RSCLK
TEST
LPBKB
Divided by 5
Clock & Data
Recovery
(PLL)
Clock
Generator
Control Logic MUX
Normal Mode
Test & Loopback
Signal
Detect
Data Transceiver Functions Block Diagram
MX98704
TDH, TDL
TXEN
RDH, RDL
SDO
SDI
5.1 NORMAL OPERATION MODE
The 5-bit data symbols to be transmitted are input from the PDTR chip on TDAT4-TDAT0.. The 5-bit symbol is latched
into the PDT by the rising edge of SYMCLK, serialized and shifted to the output (TDAT4 bit is the first bit transmitted,
and TDAT0 is the last bit transmitted). The TDH/TDL pair is connected to the serial link.
To generate the serial link data rate, the PDT uses SYMCLK as the frequency reference. All of the internal logic of PDT
runs on an internal clock that is PLL-multiplied from the external reference source. The PDT's internal PLL is referenced
to the falling edge of SYMCLK only.
The input clock frequency required to achieve 125 Mbaud on serial link is 25MHz at SYMCLK. The external TCLKIN
or external Crystal reference clock (XTAL1, XTAL2) must meet I.E.E.E. frequency and stability requirements. The PDT
serial output typically contains less than 0.4ns peak-to-peak jitters at 125 Mbaud. The latency from the SYMCLK to the
serial output is typical 4 to 6 bits (8 ns/bit).
The PDR accepts encoded NRZI serial data on the RDH/ RDL inputs. It latches the unframed symbol (5 bits) to the
RDAT4-0 outputs on the falling edge of RSCLK. Five new bits are valid on each rising edge of RSCLK. RDAT4 is the
first bit received and RDAT0 is the last bit received from the serial interface.
The heart of PDR is its clock-recovery PLL, which extracts encoded clock information from the serial NRZ data stream
and recovers the data. The PLL examines every data transition in the received serial stream and aligns its internal bit
clock with these data transitions. In order to guarntee the correct operaion of PLL, the encoding scheme (4B/5B) must
ensure adequate transition density of the encoded data stream.
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