MX98704EC Ver la hoja de datos (PDF) - Macronix International
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MX98704EC Datasheet PDF : 15 Pages
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MX98704
The SDI input qualifies the data at RDH/ RDL. When SDI is LOW, the PDR uses SYMCLK as the PLL input reference.
The LPBKB input selects the data source between RDH/ RDL and internal. When LPBKB is LOW, the SDI input is
ignored.
5.2 TRANSMIT FUNCTIONS BLOCK
The transmitter consists of several blocks:
5.2.1 CLOCK MULTIPLIER
TCLKIN or Crystal Oscillator supplies the reference frequency which is multiplied by five using an on-chip PLL. The
transmission rate and all serialization logic are controlled by the internally generated bit clock.
5.2.2 INPUT REGISTER
TDAT4-0 are clocked into the input Resister by the rising edge of SYMCLK.
5.2.3 SHIFT
Parallel data are loaded from the input Resistor into the Shifter at the internally generated symbol boundary, and serially
shifted at the bit clock rate.
5.2.4 NRZ TO NRZI CONVERTER
The NRZ output of the Shifter is converted into NRZI data patterns for transmission.
5.2.5 OUTPUT CONTROL
The differential outputs carry the encoded serial NRZI bit stream. The TDH/ TDL pair can be forced to logical 0 (TDH
LOW, TDL HIGH) by asserting TXEN input.
5.3 RECEIVER FUNCTIONS BLOCK
The receiver consists of several blocks:
5.3.1 CLOCK AND DATA RECOVERY PLL
The clock-recovery PLL separates the input data stream into clock and data patterns. The RSCLK is the recovered bit
clock divided by five. This is a 25MHz clock.
5.3.2 MEDIA INTERFACE
The RDH/ RDL inputs are typically driven by differential PECL voltages, referenced to +5V. These inputs accept the
encoded NRZI serial data.
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