MX98715 Ver la hoja de datos (PDF) - Macronix International
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MX98715 Datasheet PDF : 39 Pages
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MX98715AEC-C
Field
10
9
8
7
6
5
4
3
2
1
0
Name
ETI
RWT
RPS
RU
RI
UNF
LPANCI
TJT
TU
TPS
TI
Description
Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to
internal TX FIFO. CSR5<0> will automatically clear this bit.
Receive Watchdog Timeout, reflects the network line status where receive watchdog
timer has expired while the other node is still active on the network.
Write only, when written with any value, MX98715AEC-C reads receive descriptor list in
host memory pointed by CSR4 and processes the list.
Receive Buffer Unavailable, the receive process is suspended due to the next
descriptor in the receive list is owned by host. If no receive poll command is issued, the
reception process resumes when the next recognized incoming frame is received.
Receive Interrupt, indicating the completion of a frame reception.
Transmit Underflow, indicating transmit FIFO has run empty before the completion of a
packet transmission.
When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10
Base-T link integrity test has completed successfully, after the link was down. This bit is
also set as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report.
This bit is only valid when CSR6<18>=0, i.e. 10 Base-T port is selected Link Fail interrupt
( CSR5<12> ) will automatically clears this bit.
Transmit Jabber Timeout, indicating the MX98715 has been excessively active. The
transmit process is aborted and placed in the stopped state. TDES0<1> is also set.
Transmit Buffer Unavailable, transmit process is suspended due to the next descriptor in
the transmit list is owned by host.
Transmit Process Stopped.
Transmit Interrupt. indicating a frame transmission was completed.
P/N:PM0655
REV. 0.3, MAY. 04, 2000
17
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