MX98726 Ver la hoja de datos (PDF) - Macronix International
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MX98726 Datasheet PDF : 55 Pages
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MX98726
Packet Buffer Interface :
PIN# Pin Name
4-7,1, MA[19:3]
115-119
90-96, MD[15:0]
98-104,
106-109
114
MA2(EEDO)
Type
O,4ma
I/O,4ma
1/O,4ma
113
MA1(EEDI) 1/O,4ma
111
MA0(EECK) 1/O,4ma
87
86
88, 89
MOEB
MCSB
MWEB[1:0]
O,4ma
O,4ma
O,4ma
Description
Memory Address Bit 19-0: If HLDA = 0 then all these address lines are tri-
stated.
Memory Data Bit 15-0:
Memory Address Bit 2 or EEPROM Data Out bit: Right after host reset,
GMAC automatically load configuration information from external EEPROM.
During this period, MA2 pin acts as a EEDO pin that read in output data
stream from EEPROM. After EEPROM auto load sequence is done, this
pin becomes MA2 together with MA[19:3] forms packet buffer address
line 19 - 0. Internally pull-down.
Memory Address Bit 1 or EEPROM Data In bit: During EEPROM auto
load sequence, MA1 pin acts as EEDI pin that write data stream into
EEPROM. After EEPROM auto load sequence is done, this pin becomes
MA1, together with MA[19:2] forms packet buffer address lines.
Memory Address Bit 0 or EEPROM Clock Input : During EEPROM auto
load sequence, MA0 pin acts as EECK pin that provides clock to EEPROM.
After EEPROM auto load sequence is done, this pin becomes MA0, to-
gether with MA[19:1] forms packet buffer address lines.
Memory Output Enable: Active low during packet buffer read access.
Memory Chip Select: Active low during packet buffer accesses.
Byte Write Enable: Active low during packet buffer write cycle. MWEB1 for
high byte and MWEB0 for low byte.
P/N:PM0555
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
6
REV. 0.9.8, FEB. 14, 2000
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