datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

MX98726 Ver la hoja de datos (PDF) - Macronix International

Número de pieza
componentes Descripción
Lista de partido
MX98726 Datasheet PDF : 55 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
MX98726
3.0 Register (Default value is defined after hardware/power-up reset)
Reset logic : All register bits are cleared by hardware reset, while register bit with an "*" in its symbol
name is also cleared by software reset.
Network Control Register A : NCRA (Reg00h),R/W, default=00h
Bit
Symbol
Description
0.0
RESET
Software reset.
0.1
ST0*
Start Transmit Command/Ststus: Write to issue commands, when done both bits are
0.2
ST1*
cleared automatically.
Transmit operation: ST1 ST0
Stop Transmission 0
0
To stop transmission (if read, indicates IDLE state)
TX DMA Poll
0
1
Start TX DMA
TX FIFO Send
1
0
Immediately send the packet stored in TX FIFO
TX DMA Poll
1
1
Same as ST1=0, ST0=1.
0.3
0.4, 0.5
SR*
LB0*,LB1*
All transmit commands are cleared to "00" when operation is done ( except Stop
transmission command ). When Stop transmission command is issued, check
TXDMA[3:0] = 1h for IDLE state, making sure that internal TX state machine is in IDLE
state. TX DMA poll and TX FIFO Send can not be used at the same time. New packet
can be written to FIFO directly only when ST1, ST0=0 and TXDMA[3:0]= 1h. TX FIFO
send and TX FIFO poll commands can be issued only when ST1, ST0=IDLE and
TXDMA[3:0]=1h.
Start Transmit: Enable the MAC receive packets. Default is disabled.
Loopback Mode: LB1 LB0
Mode0
0
0
Normal mode
Mode1
0
1
Internal FIFO Loopback
Mode2
1
0
Internal NWAY Loopback
Mode3
1
1
Internal PMD Loopback
Mode 2 and 3 are reserved for IC test purpose. Only mode 1 can be used on bench.
External loopback for bench can be done by full duplex normal mode with real cable
hooked up from TX port to RX port.
0.6
INTMODE Interrupt Mode: Set for active high interrupt, reset for active low interrupt case.
0.7
CLKSEL Clock Select : Set to use internal 40MHz clock for all internal DMA, default is reset to use
internal 50MHz clock for all internal DMA.
P/N:PM0555
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
9
REV. 0.9.8, FEB. 14, 2000

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]