PCA9558 Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
Lista de partido
PCA9558 Datasheet PDF : 27 Pages
| |||
NXP Semiconductors
PCA9558
8-bit I2C-bus/SMBus I/O port
7.1.2.2 OP - Output Port register
This register is an output-only port. It reflects the outgoing logic levels of the GPIO defined
as outputs in the IOC register. Bit values in this register have no effect on GPIO defined as
inputs. In turn, reads from this register reflect the value stored in the flip-flop controlling
the output, not the actual output value.
Table 6. OP - Output Port register description
Bit
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
0
0
0
0
0
0
0
0
7.1.2.3 PI - Polarity Inversion register
This register enables polarity inversion of GPIO defined as inputs by the IOC register. If a
bit in this register is set to a logic 1, the corresponding GPIO input port is inverted. If a bit
in this register is set to a logic 0, the corresponding GPIO input port is not inverted.
Table 7. PI - Polarity Inversion register description
Bit
7
6
5
4
3
2
1
0
Symbol
P7
P6
P5
P4
P3
P2
P1
P0
Default
1
1
1
1
0
0
0
0
7.1.2.4 IOC - Input/Output Configuration register
This register configures the direction of the GPIO pins (IOx). If a bit is set to a logic 1, the
corresponding port pin is enabled as an input with a high-impedance output driver. If a bit
is set to a logic 0, the corresponding port pin is enabled as an output.
Table 8. IOC - Input/Output Configuration register description
Bit
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
1
1
1
1
1
1
1
1
Examples of read/write to these registers can be found in Figure 9, Figure 10, Figure 15,
and Figure 16.
The IO_OUT_LOW input, when held LOW longer than the time Tcy(W), will reset the GPIO
registers to their default (power-up) values.
A read of the present value of the inputs MUX_INx can be done via the I2C-bus. This is
done by addressing the PCA9558 in a write mode and entering the correct command
code. The preset value on the MUX_INx inputs is latched at the command code
Acknowledge. A REPEATED START is then sent with the R/W bit set to a logic 1, read,
and this latched data is read out on the I2C-bus. See Figure 11.
PCA9558_4
Product data sheet
Rev. 04 — 14 April 2009
© NXP B.V. 2009. All rights reserved.
9 of 27
Share Link: 