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PCA9561 Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9561
Quad 6-bit multiplexed I2C-bus EEPROM DIP switch
7.4 Bus transactions
Data is transmitted to the PCA9561 registers using the Write Byte transfers (see Figure 9
and Figure 10. Data is read from PCA9561 using Read and Receive Byte transfers (see
Figure 11).
slave address
control register
write on EEPROM byte 0
EEPROM byte 0 data
SDA S 1 0 0 1 1 A1 A0 0 A 0 0 0 0 0 0 0 0 A X X D5 D4 D3 D2 D1 D0 A P
START condition
R/W acknowledge
from slave
Fig 9. Write on one EEPROM, assuming WP = 0
acknowledge
from slave
acknowledge
from slave
STOP condition
002aah289
slave address
control register
write on EEPROM byte 0
EEPROM byte 0 data
SDA S 1 0 0 1 1 A1 A0 0 A 0 0 0 0 0 0 0 0 A X X D5 D4 D3 D2 D1 D0 A (cont.)
START condition
R/W acknowledge
from slave
acknowledge
from slave
acknowledge
from slave
EEPROM byte 1 data
(cont.) X X D5 D4 D3 D2 D1 D0 A P
Fig 10. Write on two EEPROMs, assuming WP = 0
acknowledge
from slave
STOP condition
002aah290
slave address
control register
read MUX_IN values
slave address
SDA S 1 0 0 1 1 A1 A0 0 A 1 1 1 1 1 1 1 1 A S 1 0 0 1 1 A1 A0 1 (cont.)
START condition
R/W acknowledge
from master
acknowledge ReSTART
R/W
from master
data from MUX_IN
(cont.) A 0 0 A B C D E F NA P
Fig 11. Read MUX_IN register
acknowledge
from master
no acknowledge
from master
STOP condition
002aah291
PCA9561
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 November 2012
© NXP B.V. 2012. All rights reserved.
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