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PCF8584

I2C-bus controller

NXP Semiconductors. 

Philips Semiconductors

I2C-bus controller

Product specification

PCF8584

handbook, full pagewidth

START

PCF8584 resets to

slave receiver mode

parallel bus interface

determined by

PCF8584 (80XX/68XXX)

reset minimum

30 clock cycles

send byte 80H

send byte 55H

send byte A0H

send byte 1CH

send byte C1H

power-on

address line A0

A0 = HIGH

A0 = LOW

A0 = HIGH

A0 = LOW

A0 = HIGH

initialization of

PCF8584 completed

delay: wait a time

equal to the longest I2C

message to synchronize

BB-bit. (multimaster

systems only

END

A0 = HIGH enables data transfer to/from

register S1

A0 = LOW Access to all other registers

defined by the bit pattern in

register S1

Loads byte 80H into register S1'

i.e. next byte will be loaded into register S0'

(own address register); serial interface off.

Loads byte 55H into register S0';

effective own address becomes AAH.

Loads byte A0H into register S1, i.e. next byte

will be loaded into the clock control register S2.

Loads byte 1CH into register S2;

system clock is 12 MHz; SCL = 90 kHz.

Loads byte C1H into register S1; register enable

serial interface, set I2C-bus into idle mode;

SDA and SCL are HIGH. The next write or read

operation will be to/from data transfer register

S0 if A0 = LOW.

On power-on, if an PCF8584 node is powered-up

slightly after another node has already begun an

I2C-bus transmission, the bus busy condition will

not have been detected. Thus, introducing this

delay will insure that this condition will not occur.

MBE714

1997 Oct 21

Fig.5 PCF8584 initialization sequence.

15

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