RTL8101 Ver la hoja de datos (PDF) - Unspecified
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RTL8101 Datasheet PDF : 68 Pages
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RTL8101L
destination address, 0 to reject.
5.9 9346CR: 93C46 Command Register
(Offset 0050h, R/W)
Bit
R/W
Symbol
Description
7-6
R/W
EEM1-0
Operating Mode: These 2 bits select the RTL8101L operating mode.
EEM1
0
0
1
1
EEM0
0
1
0
1
Operating Mode
Normal (RTL8101L network/host communication mode)
Auto-load: Entering this mode will make the RTL8101L
load the contents of 93C46 like when the RSTB signal is
asserted. This auto-load operation will take about 2 ms.
After it is completed, the RTL8101L goes back to the
normal mode automatically (EEM1 = EEM0 = 0) and all
the other registers are reset to default values.
93C46 programming: In this mode, both network and
host bus master operations are disabled. The 93C46 can
be directly accessed via bit3-0 which now reflect the
states of EECS, EESK, EEDI, & EEDO pins respectively.
Config register write enable: Before writing to CONFIG0,
1, 3, 4 registers, and bit13, 12, 8 of BMCR(offset
62h-63h), the RTL8101L must be placed in this mode.
This will prevent RTL8101L's configurations from
accidental change.
4-5
-
3
R/W
2
R/W
1
R/W
0
R
-
EECS
EESK
EEDI
EEDO
Reserved
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in
auto-load or 93C46 programming mode.
5.10 CONFIG 0: Configuration Register 0
(Offset 0051h, R/W)
Bit
R/W
Symbol
Description
7
R
SCR
Scrambler Mode: Always 0.
6
R
PCS
PCS Mode: Always 0.
5
R
T10
10 Mbps Mode: Always 0.
4-3
R
PL1, PL0
Select 10 Mbps Medium Type: Always (PL1, PL0) = (1, 0)
2-0
R
BS2, BS1, BS0 Select Boot ROM size (Autoloaded from EEPROM)
BS2
BS1
BS0
Description
0
0
0
No Boot ROM
0
0
1
8K Boot ROM
0
1
0
16K Boot ROM
0
1
1
32K Boot ROM
1
0
0
64K Boot ROM
1
0
1
128K Boot ROM
1
1
0
unused
1
1
1
unused
5.11 CONFIG 1: Configuration Register 1
2003-05-28
20
Rev.1.3
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