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RTL8130

REALTEK SINGLE CHIP FAST ETHERNET CONTROLLER WITH MII & AUI INTERFACE

Realtek Semiconductor 

RTL8130 Preliminary

5.8 Receive Configuration Register (Offset 0044h-0047h, R/W)

Bit

31-28

27-24

23-18

17

16

15-13

12-11

R/W

-

R/W

-

R/W

R/W

R/W

R/W

Symbol

-

ERTH3, 2, 1, 0

-

MulERINT

RER8

RXFTH2, 1, 0

RBLEN1, 0

Description

Reserved

Early Rx threshold bits: These bits are used to select the Rx threshold

multiplier of the whole packet that has been transferred to the system

buffer in early mode when the frame protocol is under the RTL8130's

definition.

0000 = no early rx threshold

0001 = 1/16

0010 = 2/16

0011 = 3/16

0100 = 4/16

0101 = 5/16

0110 = 6/16

0111 = 7/16

1000 = 8/16

1001 = 9/16

1010 = 10/16

1011 = 11/16

1100 = 12/16

1101 = 13/16

1110 = 14/16

1111 = 15/16

Reserved

Multiple early interrupt select:

When this bit is set, any received packet invokes early interrupt

according to MULINT<MISR[11:0]> setting in early mode.

When this bit is reset, the packets of familiar protocol (IPX, IP, NDIS,

etc) invoke early interrupt according to RCR<ERTH[3:0]> setting in

early mode. The packets of unfamiliar protocol will invoke early

interrupt according to the setting of MULINT<MISR[11:0]>.

The RTL8130 receives the error packet whose length is larger than 8

bytes after setting the RER8 bit to 1.

The RTL8130 receives the error packet larger than 64-byte long when

the RER8 bit is cleared. The power-on default is zero.

If AER or AR is set, the RER will be set when the RTL8130 receives

an error packet whose length is larger than 8 bytes. The RER8 is

“ Don’t care “ in this situation.

Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the

number of the received data bytes from a packet, which is being

received into the RTL8130's Rx FIFO, has reached to this level (or the

FIFO has contained a complete packet), the receive PCI bus master

function will begin to transfer the data from the FIFO to the host

memory. This field sets the threshold level according to the following

table:

000 = 16 bytes

001 = 32 bytes

010 = 64 bytes

011 = 128 bytes

100 = 256 bytes

101 = 512 bytes

110 = 1024 bytes

111 = no rx threshold. The RTL8130 begins the transfer of data after

having received a whole packet in the FIFO.

Rx Buffer Length: This field indicates the size of the Rx ring buffer.

00 = 8k + 16 byte

01 = 16k + 16 byte

10 = 32K + 16 byte

1999/5/30

15

Ver.1.1

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