RTL8130 Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8130 Datasheet PDF : 55 Pages
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4-5
-
3
R/W
2
R/W
1
R/W
0
R
-
EECS
EESK
EEDI
EEDO
RTL8130 Preliminary
bus master operations are disabled. The 93C46 can be
directly accessed via bit3-0 which now reflect the states of
EECS, EESK, EEDI, & EEDO pins respectively.
1
1
Config register write enable: Before writing to CONFIG0,
1 registers, the RTL8130 must be placed in this mode.
This will prevent RTL8130's configurations from
accidental change.
Reserved
These bits reflect the state of EECS, EESK, EEDI & EEDO pins in
auto-load or 93C46 programming mode and are valid only when
Flash bit is cleared.
Note: EESK, EEDI and EEDO is valid after boot ROM complete.
5.10 CONFIG 0: Configuration Register 0 (Offset 0051h, R/W)
Bit
R/W
Symbol
Description
7
R
SCR
Scrambler Mode: Always 0.
6
R
PCS
PCS Mode: Always 0.
5
R
T10
10 Mbps Mode: Always 0.
4-3
R
PL1, PL0
Select 10 Mbps medium type: Always (PL1, PL0) = (1, 0)
2-0
R
BS2, BS1, BS0 Select Boot ROM size
BS2
BS1
BS0
Description
0
0
0
No Boot ROM
0
0
1
8K Boot ROM
0
1
0
16K Boot ROM
0
1
1
32K Boot ROM
1
0
0
64K Boot ROM
1
0
1
128K Boot ROM
1
1
0
unused
1
1
1
unused
5.11 CONFIG 1: Configuration Register 1 (Offset 0052h, R/W)
Bit
R/W
Symbol
Description
7-6
R/W
LEDS1-0 Refer to LED PIN definition. These bits initial value com from 93C46.
5
R/W
DVRLOAD Driver Load: Software maybe use this bit to make sure that the driver has been
loaded. Writing 1 is 1. Writing 0 is 0. When the command register bits IOEN,
MEMEN, BMEN of PCI configuration space are written, the RTL8130 will
clear this bit automatically.
1999/5/30
17
Ver.1.1
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