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SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

Description of deflection part

LLDFL

The input signal LLDFL is the main line-locked clock pulse

for the deflection side of the memory controller generated

by an external PLL circuit. The frequency of LLDFL is

always 27 MHz and is independent of the chosen feature

modes. The PLL circuit operates on the video clamping

pulse CLV of the acquisition part and the horizontal

reference signal HRDFL generated by the deflection side

of SAA4951.

HRDFL

This horizontal output signal is the reference pulse for the

horizontal deflection drive signal HDFL. The duty cycle of

HRDFL is 50% and the cycle time is 64 µs (PAL). In case

of golden scart mode the cycle time is reduced to 32 µs.

HDFL

The output signal HDFL is aimed for driving the connected

horizontal deflection circuit. HDFL has a cycle time of

32 µs and a pulse width of 64 x LLDFL = 2.37 µs

handbook, full pagewidth

HRDFL

HDFL

864/858 × LLDFL (50/60 Hz)

432/429 × LLDFL (50/60 Hz)

64 × LLDFL

64 × LLDFL

MGH139

Fig.10 Horizontal deflection timing.

VDFL

This is the vertical synchronization output signal generated

by the acquisition side of SAA4951. The timing reference

of VDFL is the LOW-to HIGH transition of the vertical

acquisition input pulse VACQ. Normally VDFL has a pulse

width of 2.5 x HDFL = 80 µs and a cycle time of 100 Hz.

In normal mode the memory controller operates with two

field memories and 100 Hz interlace picture reproduction.

When the system includes only one field memory it is

necessary to activate the AABB mode. In the simple field

repetition mode the first two and the last two 100 Hz fields

are out one upon another

Description of control inputs/outputs

ALE

The address latch enable input signal ALE is provided by

the microcontroller. A falling edge of ALE denotes a valid

address.

WRD

This is the write/read enable control signal supplied by the

microcontroller. The HIGH-to-LOW transition of WRD

indicates valid data.

P0 to P7

The SAA4951 is controlled by the bidirectional port bus

P0.0 to P0.7 of a microcontroller. Address and data are

transmitted sequentially on the bus.

TEST

The TEST input pin has to be connected to ground.

April 1994

18

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