SAA4951 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Lista de partido

SAA4951

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Preliminary specification

SAA4951

FUNCTIONAL DESCRIPTION

Block diagram and short description

The SAA4951 is a memory controller intended to be used

for scan conversion in TV receivers. This conversion is

done from 50 to 100 Hz or from 60 to 120 Hz. The device

supports three separate PLL circuits: the acquisition PLL

can run on 12, 13.5, 16 or 18 MHz, the display PLL on 27,

32 or 36 MHz, and the deflection PLL on 27 MHz. This

allows frequency doubling for input data rates of 13.5, 16

and 18 MHz. For displaying a 4:3 picture on a 16:9 screen

additional horizontal compression is possible when using

the clock configuration 12/32 MHz and 13.5/36 MHz. The

VCO and loop filter are peripheral parts of each PLL, the

clock divider and generation of the reference pulse for the

phase detector are internally provided.

The device generates all write, read and clock pulses to

operate a field memory in a desired mode. The required

signals are programmable via an 8-bit parallel

microcontroller port.

The block diagram of the SAA4951 is shown in Fig.3. The

clock signal from the VCO is fed in at pin 13, a horizontal

reference pulse for the phase discriminator is fed out at

pin 11.

By setting the clock divider to different values the PLL can

be forced to run on different clock frequencies.

Besides this the acquisition part can also be configured to

run on a fixed input clock. Then pin 11 is an input pin, so

the horizontal reference pulse can be supplied from the

outside. This mode is intended to be used together with a

digital decoder which is providing clock and reference

pulses.

In the horizontal processing part the signals WE1, WE2

and CLV are generated. The vertical processing block

supplies the signals RSTW1 and RSTW2 as well as

enable signals for the horizontal part. The start and stop

position of the pulses are programmable, the increment

being 4 clock cycles in the horizontal part and 1 line in the

vertical part. For WE1 and WE2 an additional 2-bit fine

delay is available.

Display related control signals are derived from the display

PLL. The functions are similar to the acquisition part. The

PLL can be switched to 32 or 36 MHz, in case of 27 MHz

this clock is taken from the deflection PLL which always

runs on 27 MHz. In the horizontal part the pulse WE2,

RE1, RE2 and BLN are programmable in increments of 4

clock cycles, each one adjustable by an additional 2-bit

fine delay. The vertical processing block generates VDFL,

RSTW2 and enable signals for the horizontal part.

The deflection PLL runs on 27 MHz. From this clock the

16 kHz PLL reference pulse HRDFL is generated as well

as the 32 kHz deflection pulse HDFL.

In the vertical acquisition part the distance between the

incoming 50 Hz vertical synchronization pulse VACQ and

the horizontal synchronization pulse CLV generated by the

horizontal deflection circuit is measured. In addition the

field length is calculated by the acquisition counter, which

is enabled by CLV.

A fixed vertical reset pulse RSTW1 and a programmable

vertical control of the write enable pulse WE1 for

memory 1 defining the vertical write window are

generated.

In the display section the programmable 100 Hz write

enable pulse WE2 for the memory 2 and the

programmable 100 Hz read enable pulses RE1 and RE2

are provided. The 100 Hz vertical synchronizing signal

VDFL is corrected by the calculated values of the

acquisition part. The position of this pulse can also be

chosen by the microcontroller. Furthermore two field

identification signals for 50 Hz and for 100 Hz are

generated internally to mark the corresponding fields by

the microcontroller.

April 1994

6

Share Link: