SC92031 Ver la hoja de datos (PDF) - Silan Microelectronics

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componentes Descripción

Lista de partido

SC92031

10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER

Silan Microelectronics 

PIN CONFIGURATION

SC92031

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ACT 76

50 CLKR

G_RST 77

49 AUX

REQB2 78

48 EECS

GNTB2 79

47 EECK

SE 80

46 EEDI

INTAB 81

45 EEDO

RSI_RST 82

44 AD0

PCI_CLK 83

43 AD1

VDD 84

42 VDD

GNTB 85

41 AD2

REQB 86

40 AD3

PMEB 87

AD31 88

SC92031L

39 GND

38 GND

AD30 89

37 AD4

GND 90

36 AD5

AD29 91

35 AD6

AD28 92

34 ROM_OE

AD27 93

33 VDD

AD26 94

32 AD7

AD25 95

31 C/BE0B

AD24 96

30 GND

VDD 97

29 AD8

C/BE3B 98

28 AD9

IDSEL 99

27 AD10

AD23 100

26 AD11

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

PIN DESCRIPTION

Pin No.

PCI Interface

Symbol

82

PCI_RST

83

PCI_CLK

88, 89, 91-96,

100, 1, 3-5, 7-9,

22-29, 32, 35-

37, 40, 41, 43,

44

AD31-0

Description

When RSTB is asserted low, the SC92031 performs internal system

hardware reset. RSTB must be held for a minimum of 120 ns.

This PCI Bus clock provides timing for all transactions and bus phases, and

is input to PCI devices. The rising edge defines the start of each phase. The

clock frequency ranges from 0 to 33MHz.

PCI address and data multiplexed pins.

Pins AD31-24 are shared with Boot ROM data pins, while AD16-0 are

shared with Boot ROM address pins.

(To be continued)

HANGZHOU SILAN MICROELECTRONICS CO.,LTD

Http: www.silan.com.cn

REV:1.0 2004.08.03

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