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GM16C550

ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFOs

Hynix Semiconductor 

Status Register indicates whether the RI input signal

has changed from a low to a high state since the previous

reading of the MODEM Status Register

Note : Whenever the RI bit of the MODEM Status Regi-

ster changes from a high to a low state, an inter-

rupt is generated if the MODEM Status Interrupt

is enabled.

Vcc, Pin 40 : +5V supply.

Vss, Pin 20 : Ground(0V) reference.

OUTPUT SIGNALS

Data Terminal Ready ( DTR ), Pin 33: When low, this

informs the MODEM or data set that the UART is ready to

establish communications link. The DTR output signal

can be set to an active low by programming bit 0 (DTR) of

the MODEM Control Register to high level. A Master

Reset operation sets this signal to its inactive (high) state.

Loop mode operation holds this signal in its inactive state.

Request to Send ( RTS ), Pin 32: When low, this informs

the MODEM and data set that the UART is ready to

exchange data. The RTS output signal can be set to an

active low by programming bit 1 (RTS) of the MODEM

Control Register. A Master Reset operation sets this signal

to its inactive state. Loop node operation holds this signal

in its inactive state.

Output 1 ( OUT1 ), Pin 34: This user-designed out-put

can be set to an active low by programming bit 2 (OUT1)

of the MODEM Control Register to a high level. A Master

Reset operation sets this signal to its inactive state. Loop

Mode operation holds this signal to its inactive state.

Output 2 ( OUT2 ), Pin 31: This user-designated output

can be set to an active low by programming bit 3 (OUT2)

of the MODEM Control Register to a high level. A Master

Reset operation sets this signal to its inactive (high) state.

Loop mode operation holds this signal to its inactive state.

TXRDY, RXRDY, Pin 24, 29: Transmitter and Receiver

DMA signaling is available through two pins (24 and 29).

When operating in the FIFO mode, one of two types DMA

signaling per pin can be selected via FCR3, When

operating as in the GM16C16450 Mode., only DMA Mode

0 is allowed. Mode 0 supports single transfer DMA where

a transfer is made between CPU bus cycles. Mode 1

supports multi-transfer DMA where multiple transfers ard

made continuously until the RCVR FIFO has been

emptied or the XMIT FIFO has been filled.

RXRDY Mode 0: When in the GM16C450 Mode (FCR0 =

0) or in the FIFO Mode (FCRO = 1, RCR3 = 0) and there is

at least 1 character in the RCVR FIFO of RCVR holding

register, the RXRDY pin (29) will be low active. Once it is

activated the RXRCY pin will go inactive when there are no

more characters in the FIFO of holding register.

GM16C550

RXRDY Mode 1: In the FIFO Mode (FCR0 = 1) when the

FRC3 = 1 and the trigger level or the timeout has been

reached, the RXRDY pin will go low active. Once it is

activated it will go inactive when there are no more characters

in the FIFO or holding register.

TXRDY Mode 0: in the GM16C450 Mode (FCR0 = 0) or in

the FIFO Mode (FCR = 1, FCR3 = 0) and there are no

characters in the XMIT FIFO or XMIT hold register, the

TXRDY pin(24) will be low active. Once it is activated the

TXRDY pin will go inactive after the first character is loaded

into the XMIT FIFO or holding register.

TXRDY Mode 1: In the FIFO Mode (FCR0 = 1) when

FCR3 = 1 and there is at least one unfilled position in the

XMIT FIFO, it will go low active. This pin will become

inactive when the XMIT FIFO is completely full.

Driver Disable (DDIS), Pin 23: this goes low whenever

the CPU is reading data from the UART. It can disable or

control the direction of a data bus transceiver between the

CPU and the UART.

Baud Out ( BAUDOUT ), Pin 23: This is the 16X clock

signal from the transmitter section of the UART. The clock

rate is equal to the main reference oscillator frequency

divided by the specified divisor in the Baud Generator

Divisor Latches. The BAUDOUT may also be used for

the receiver section by tying this output to the RCLK input

of the chip.

Interrupt (INTR), Pin 30: This pin goes high when-ever

any one of the following interrupt types has an active high

cognition and is enabled via the IER; Receiver Error Flag;

Received Data Avail-able; timeout (FIFO Mode only);

Transmitter Holding Register Empty; and MODEM Status,

The INTR signal is reset low upon the appropriate

interrupt service or a Master Reset operation.

Serial output (SOUT), Pin 11: Composite serial data

output to the communications link (peripheral. MODEM

or data set). The SOUT signal is set to the Marking (logic

1) state upon a Master Reset operation.

INPUT / OUTPUT SIGNALS

Data (D7-D0) Bus, Pin 1-8: This bus comprises eight

TRI-state input/output lines. The bus provides bi-

directional communications between the UART and the

CPU, Data, control words. And status information are

transferred via the D7-D0 Data Bus.

External Clock Input/Output (XIN, XOUT), Pins 16 and

17: These two pins connect the main timing reference (crystal

or signal clock) to the UART.

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