GM16C550 Ver la hoja de datos (PDF) - Hynix Semiconductor
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GM16C550 Datasheet PDF : 22 Pages
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GM16C550
Bit 0: Writing a 1 to FCR0 enables both the XMIT and
RCVR FIFOs. Resetting FCR0 will clear all bytes in both
FIFOs. When changing from FIFO Mode to GM16C450
Mode and vice versa, data is automatically cleared from the
FIFOs. This bit must be a 1 when other RCR bits are written
to or they will not be programmed.
Bit 1: Writing a 1 to FCR1 clears all bytes in the RCVR FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-
clearing.
Bit 2: Writing a 1 to FCR2 clears all bytes in the XMIT FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-
clearing.
Bit 3: Setting FCR 3 to a 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1 if FCR0 = 1
(see description of RXRDY and TXRDY pins).
Bit4, 5: FCR4 to FCR5 are reserved for future use.
Bit6, 7: FCR6 to FCR7 are used to set the trigger level for the
RCVR FIFO interrupt.
7
6
0
0
0
1
1
0
1
1
RCVR FIFO
Trigger Level
(Bytes)
01
04
08
14
INTERRUPT IDENTIFICATION
REGISTER
In order to provide minimum software overhead during data
character transfers, the UART prioritizes interrupts into four
levels and records these in the interrupt Identification Register.
The four levels of interrupt conditions in order of priority are
Receiver Line Status; Received Data Ready; Transmitter
Holding Register Empty; and MODEM Status. When the
CPU accesses the IIR, the UART freezes all interrupts and
indicates the highest priority pending interrupt to the CPU.
While this CPU access is occurring, the UART records niw
interrupts, but access is complete. Table II shows the contents
of the IIR. Details on each bit follow:
Bit 0: This bit can be used in a prioritized interrupt
environment to indicate whether an interrupt is pending.
When bit 0 is a logic 0, an interrupt is pending and the IIR
contents may be used as a pointer to the appropriate interrupt
service routine. When bit 0 is a logic 1, no interrupt is
pending.
Bit 1 and 2: These two of the IIR are used to identify
highest priority interrupt pending as indicated in Table VI.
Bit 3: In the GB16C450 Mode this bit is 0. In the FIFO mode
this bit is set along with bit 2 when a timeout interrupt is
pending.
Bit 4 and 5: These two bits of the IIR are always logic 0.
Bit 6 and 7: These two bits are set when FCR0 =1.
INTERRUPT ENABLE REGISTER
This register enables the five types of UART interrupts. Each
interrupt can individually activate the interrupt (INTR) output
signal. It is possible to totally disable the interrupt system by
resetting bits 0 through 3 of the Interrupt Enable Register
(IER).
Similarly, setting bits of the IER register to a logic 1, enables
the selected interrupt(s). Disabling an interrupt prevents it
from being indicated as active in the IIR and from activating
the INTR output signal. All other system functions operate in
their normal manner, including the setting of the Line Status
and MODEM Status Registers. Table II shows the contents of
the IER. Details on each bit follow.
Bit 0: This bit enables the Received Data Available Interrupt
(and timeout interrupts in the FIFO mode) when set to logic1.
Bit 2: This bit enables the Receiver Line Status interrupt
when set to logic 1
Bit 3: This bit enables the MODEM Status interrupt when set
to logic 1
Bit 4 through 7: These four bits are always logic 0.
MODEM CONTROL REGISTER
This register controls the interface with the MODEM or data
set (or peripheral device emulating a MODEM). The contents
of the MODEM Control Register are indicated in Table II and
are described below.
Bit 0: This bit controls the Data Terminal Ready
(DTR) output. When bit 0 is set to a logic 1, the DTR output
is forced to a logic 0. When bit 0 is reset to a logic 0, the DTR
output is forced to a logic 1.
Note: The DTR output of the UART may be applied to
an EIA inverting line driver (such as the GD751-
88) to obtain the proper polarity input at the succ-
eeding MODEM or data set.
Bit 1: This bit controls the Request to Send (RTS) output. Bit
1 affects the RTS output in a manner identical to that
described above for bit 0.
Bit 2: This bit controls the output 1 (OUT1) signal , which is
an auxillary user-designated output. Bit 2 affects the OUT1
output in a manner identical to that described above for bit 0.
Bit 3: This bit controls the output 2(OUT2) signal, which is
an auxillary user-designated output . Bit 3 affects the OUT2
output in a manner identical to that described above for bit 0.
Bit 4: This bit provides a local loopback feature for
Diagnostic testing of the UART. When bit 4 is set to logic 1,
the following occur ; the transmitter Serial output (SOUT) is
set to the Marking (logic 1) State; the receiver Serial Input
(SIN) is disconnected; the output of the Transmitter Shift
20
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