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SAA7157

Clock signal generator circuit for digital TV systems (SCGC)

Philips Electronics 

Philips Semiconductors

Clock signal generator circuit for digital TV

systems (SCGC)

Product specification

SAA7157

handbook, full pagewidth

MS

1

11

LFCO

19

LFCO2

2

CE

VDDA VDDD1 VDDD2

5

8

17

LOOP

FILTER

MS = LOW

VCO

SAA7157

PHASE

DETECTOR

FREQUENCY

DIVIDER

1:2

PRE-FILTER

AND

PULSE

SHAPER

POWER-ON

RESET

FREQUENCY

DIVIDER

1:2

DELAY

7

LL1.5A

(LL27A)

10

LL1.5B

(LL27B)

14

LL3A

20

LL3B

15

CREF

12

RESN

16

LFCOSEL

3

PORD

4

VSSA

6, 9, 13, 18

VSSD

MEH452

Fig.1 Block diagram.

FUNCTIONAL DESCRIPTION

The SAA7157 generates all clock signals required for a

digital TV system suitable for the SAA715x family

consisting of an 8-bit analog-to-digital converter (ADC8),

digital video multistandard decoder (DMSD2) and video

enhancement and D/A processor circuit (VEDA). Optional

extras (feature box, video memory etc.) can be driven via

external buffers, advantageous for a digital TV system

based on display standard conversion concepts.

The 6.75 MHz input signal LFCO (triangular waveform)

coming from the DMSD or LFCO2 is multiplied to 27 MHz

by the PLL (including phase detector, loop filter, VCO and

frequency divider) and output on LL1.5A (pin 7) and

LL1.5B (pin 10). The 13.5 MHz frequencies are generated

by dividers using ratio of 1:2 and are output on LL3A (pin

14) and LL3B (pin 20).

The rectangular output signals have 50% duty factor.

Outputs with equal frequency may be connected together

externally. The clock outputs go HIGH during power-on

reset (and chip enable) to ensure that no output clock

signals are available before the PLL has locked-on.

Mode select MS

The LFCO input signal is directly connected to the VCO at

MS = HIGH. The circuit operates as an oscillator and

frequency divider. This function is not tested.

Source select LFCOSEL

Line frequency control signal (LFCO) is selected by

LFCOSEL input.

LFCOSEL = LOW:

signal from LFCO (pin 11) is selected.

LFCOSEL = HIGH:

signal from LFCO2 (pin 19) is selected.

This function is not tested.

Chip enable CE

The buffer outputs are enabled and RESN is set to HIGH

by

CE = HIGH (Fig.4).

CE = LOW sets the clock outputs HIGH and RESN output

LOW.

May 1992

3

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