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SAA7157

Clock signal generator circuit for digital TV systems (SCGC)

Philips Electronics 

Philips Semiconductors

Clock signal generator circuit for digital TV

systems (SCGC)

Product specification

SAA7157

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Output signals LL1.5A, LL1.5B, LL3A and LL3B (pins 7, 10, 14, and 20); note 3

VOL

VOH

tcomp

fLL

output voltage LOW

output voltage HIGH

composite rise time

output frequency LL1.5A

output frequency LL1.5B

IO L = 2 mA

0

IOH = −0.5 mA

2.6

Fig.3; notes 1 and 2 -

Fig.3

-

-

output frequency LL3A

-

output frequency LL3B

-

tr, tf

rise and fall times

note 1; Fig.3

-

tLL

duty factor LL1.5A, LL1.5B, LL3A

note 1; Fig.3;

and LL3B (mean values)

at 1.5 V level

43

-

0.6

-

VDDD

-

8

4 fLFCO(2)

4 fLFCO(2)

2 fLFCO(2)

2 fLFCO(2)

-

5

V

V

ns

MHz

MHz

MHz

MHz

ns

50

57

%

Notes

1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together.

2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter

components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more

than ±2 ns if output loads are matched within 20%.

3. MS and LFCO2 functions not tested.

handbook, full pagewidth

CREF

LL1.5A

LL1.5B

LL3A

LL3B

tcomp

tHD

tSU

tHD

tLL1.5

tLL1.5H

tLL1.5L

tf

tLL3

tLL3H

tr

tLL3L

tf

2.4 V

0.6 V

2.6 V

1.5 V

0.6 V

2.6 V

1.5 V

0.6 V

tr

MEH456

May 1992

Fig.3 Output timing.

7

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