72605L20 Ver la hoja de datos (PDF) - Integrated Device Technology

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72605L20

CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

Integrated Device Technology 

IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

CLKA

COMMERCIAL TEMPERATURE RANGE

A0 , A1 , A2 ,

R/WA

tCS

CSA , ENA

DA0 -DA17

tDS

D0 (First valid write)

D1

D2

D3

tSKEW1

tFRL

(1)

CLKB

R/WB

ENB

EFAB

DB0 -DB17

OEB

tEF

tOLZ

tCS

tA

t OE

tA

D0

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1

tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timing applies only at the Empty Boundary (EF = LOW).

Figure 8. A→B First Data Word Latency after Reset for Simultaneous Read and Write

D1

2704 drw 12

5.18

14

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