72605L20 Ver la hoja de datos (PDF) - Integrated Device Technology

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72605L20

CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

Integrated Device Technology 

IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

CLKA

A0 , A1 , A2 ,

A2 , A1 , A0 , = 001

COMMERCIAL TEMPERATURE RANGE

tCS

R/WA

CSA

ENA

FFAB

DA0 -DA17

CLKB

tCS

tCH

tFF

tDS

tSKEW1

DATA INPUT

tFF

BYPASS FLAG

tSKEW1

tCH

tFF

FIFO FLAG

tSKEW1

R/WB

ENB

EFAB

tEF

FIFO FLAG

tCS

tEF

tEF

BYPASS FLAG

FIFO FLAG

BYPB

DB0 -DB17

OEB

tOLZ

tA

tOE

DATA OUTPUT

tOHZ

2704 drw 14

NOTES:

1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.

2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for

the next bypass operation.

3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be

forced back to FIFO mode.

Figure 10. A→B Bypass Timing

5.18

16

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