72605L20 Ver la hoja de datos (PDF) - Integrated Device Technology

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72605L20

CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

Integrated Device Technology 

IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

ENB

(R/W A = 0)

PAEBA

CLKA

tCLKH

tCLKL

t CS

tCH

WRITE

n words in FIFO

tSKEW2 (1)

tPAE

ENA

(R/W A = 1)

n+1 words in FIFO

(2)

tCS

tCH

tPAE

READ

2704 drw 18

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the

rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.

2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.

Figure 14. B→A Programmable Almost-Empty Flag Timing

CLKB

ENB

(R/W A = 0)

PAFBA

CLKA

t CLKH

tCLKL

t CS

(2)

tCH

WRITE

Full - (m+1) words in FIFO

tPAF

ENA

(R/W A = 1)

Full - m words in FIFO

tSKEW2 (1)

tPAF

tCS

t CH

READ

2704 drw 19

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the

rising edge of CLKB and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.

2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.

Figure 15. B→A Programmable Almost-Full Flag Timing

5.18

19

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