UT0.25UCRH Ver la hoja de datos (PDF) - Aeroflex UTMC

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UT0.25UCRH

Commercial RadHard™ Structured Array

Aeroflex UTMC 

ASIC DESIGN SOFTWARE

Using a combination of state-of-the-art third-party and

proprietary design tools, Aeroflex UTMC delivers the CAE

support and capability to handle complex, high-performance

ASIC designs from design concept through design verification

and test.

Aeroflex UTMC’s flexible circuit creation methodology

supports high level design by providing UT0.25µCRH

libraries for Mentor Graphics and Synopsys synthesis tools.

Design verification is performed in any VHDL or Verilog

simulator or the Mentor Graphics environment, using Aeroflex

UTMC’s robust libraries. Aeroflex UTMC also supports

Automatic Test Program Generation to improve design

testing.

Aeroflex UTMC HDL DESIGN SYSTEMS

Aeroflex UTMC offers a Hardware Description Language

(HDL) design system supporting VHDL and Verilog. Both the

VHDL and Verilog libraries provide sign-off quality models

and robust tools.

High Level Design Activities

Synopsys

VSS/VCS

HDL Tool

Supplier

Mentor

ModelSim

Cadence

Leapfrog /

Verilog XL

UTMC HDL

Design System

Viewlogic

SpeedWave/

VCS

The VHDL libraries are VITAL 3.0 compliant, and the

Verilog libraries are OVI 1.0 compliant.With the library

capabilities Aeroflex UTMC provides, you can use High Level

Design methods to synthesize your design for simulation.

Aeroflex UTMC also provides tools to verify that your HDL

design will result in working ASIC devices.

Either of Aeroflex UTMC’s HDL design system lets you

easily access Aeroflex UTMC’s RadHard capabilities.

ADVANTAGES OF THE AEROFLEX UTMC HDL

DESIGN SYSTEMS

• The Aeroflex UTMC HDL Design System gives you the

freedom to use tools from Synopsys, Mentor Graphics,

Cadence, Viewlogic, and other vendors to help you

synthesize and verify a design.

• Aeroflex UTMC’s Logic Rules Checker and Tester Rules

Checker allow you to verify partial or complete designs

for compliance with Aeroflex UTMC design rules.

• Aeroflex UTMC HDL Design System accepts back-

annotation of timing information through SDF.

• Your design stays entirely within the language in which

you started (VHDL or Verilog) preventing conversion

headaches.

XDTsm (eXternal Design Translation)

Through Aeroflex UTMC’s XDT services, customers can

convert an existing non-Aeroflex UTMC design to Aeroflex

UTMC’s processes. The XDT tool is particularly useful for

converting an FPGA to an Aeroflex UTMC radiation-tolerant

gate array. The XDT translation tools convert industry

standard netlist formats and vendor libraries to Aeroflex

UTMC formats and libraries. Industry standard netlist formats

supported by Aeroflex UTMC include:

• VHDL

• Verilog HDLTM

• FPGA source files (Actel, Altera, Xilinx)

• EDIF

• Third-party netlists supported by Synopsys

Completed

ASIC Design

Aeroflex UTMC HDL Design Flow

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