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UT0.25UCRH

Commercial RadHard™ Structured Array

Aeroflex UTMC 

PHYSICAL DESIGN

Using five layers of metal interconnect, Aeroflex UTMC

achieves optimized layouts that maximize speed of critical nets,

overall chip performance, and design density up to 3,000,000

equivalent gates.

Test Capability

Aeroflex UTMC supports all phases of test development from

test stimulus generation through high-speed production test.

This support includes ATPG, fault simulation, and fault grading.

Scan design options are available on all UT0.25µCRH storage

elements. Automatic test program development capabilities

handle large vector sets for use with Aeroflex UTMC’s LTX/

Trillium MicroMasters, supporting high-speed testing (up to

80MHz with pin multiplexing).

Unparalleled Quality and Reliability

Aeroflex UTMC is dedicated to meeting the stringent perfor-

mance requirements of aerospace and defense systems

suppliers. AeroflexUTMC maintains the highest level of quality

and reliability through our Quality Management Program under

MIL-PRF-38535 and ISO-9001. In 1988, we were the first gate

array manufacturer to achieve QPL certification and qualifica-

tion of our technology families. Our product assurance program

has kept pace with the demands of certification and

qualification.

Our quality management plan includes the following activities

and initiatives.

• Quality improvement plan

• Failure analysis program

• SPC plan

• Corrective action plan

• Change control program

• Standard Evaluation Circuit (SEC) and Technology Charac-

terization Vehicle (TCV) assessment program

• Certification and qualification program

Because of numerous product variations permitted with custom-

er specific designs, much of the reliability testing is performed

using a Standard Evaluation Circuit (SEC) and Technology

Characterization Vehicle (TCV). Aeroflex UTMC utilizes the

wafer foundry’s data from TCV test structures to evaluate hot

carrier aging, electromigration, and time dependent test samples

for reliability testing. Data from the wafer-level testing can pro-

vide rapid feedback to the fabrication process, as well as

establish the reliability performance of the product before it is

packaged and shipped.

Radiation Tolerance

Aeroflex UTMC incorporates radiation-tolerance techniques in

process design, design rules, array design, power distribution,

and library element design. All key radiation-tolerance process

parameters are controlled and monitored using statistical meth-

ods and in-line testing.

PARAMETER

Total dose

Dose rate upset

Dose rate

survivability

SEU

Projected

neutron fluence

Latchup

RADIATION

TOLERANCE

1.0E5 rad(SiO2)

3.0E5 rad(SiO2)

1.0E8 rad(Si)/sec

1.0E11 rad(Si)/sec

<2.0E-10 errors per cell-day

1.0E14 n/sq cm

Latchup-immune over speci-

fied use conditions

NOTES

1

2

3

4

4, 5

Notes:

1. Total dose Co-60 testing is in accordance with MIL-STD-883,

Method 1019. Data sheet electrical characteristics guaranteed to 1.0E5

rads(Si O2). All post-radiation values measured at 25 °C.

2. Total dose Co-60 testing is in accordance with MIL-STD-883,

Method 1019 at dose rates >1 rad(SiO2)/s.

3. Short pulse 20ns FWHM (full width, half maximum).

4. Is design dependent; SEU limit based on standard evaluation circuit at 4.5V

worst case condition.

5. SEU-hard flip-flop cell. Non-hard flip-flop typical is 4E-8.

7

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