W83627SF Ver la hoja de datos (PDF) - Winbond
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W83627SF Datasheet PDF : 116 Pages
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W83627SF
6.2.3 Handshake Control Register (HCR) (Read/Write) ................................................................35
6.2.4 Handshake Status Register (HSR) (Read/Write) .................................................................36
6.2.5 UART FIFO Control Register (UFR) (Write only) .................................................................37
6.2.6 Interrupt Status Register (ISR) (Read only)..........................................................................38
6.2.7 Interrupt Control Register (ICR) (Read/Write) ......................................................................39
6.2.8 Programmable Baud Generator (BLL/BHL) (Read/Write) ....................................................39
6.2.9 User-defined Register (UDR) (Read/Write) ..........................................................................40
7. CIR RECEIVER PORT................................................................................................................. 41
7.1 CIR Registers ..................................................................................................................... 41
7.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read).......................................................41
7.1.2 Bank0.Reg1 - Interrupt Control Register (ICR).....................................................................41
7.1.3 Bank0.Reg2 - Interrupt Status Register (ISR) ......................................................................41
7.1.4 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)....42
7.1.5 Bank0.Reg4 - CIR Control Register (CTR)...........................................................................42
7.1.6 Bank0.Reg5 - UART Line Status Register (USR) ................................................................43
7.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG)................................................44
7.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) .............................................................45
7.1.9 Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) ..........................................................45
7.1.10 Bank1.Reg2 - Version ID Register I (VID) ............................................................................46
7.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3)....46
7.1.12 Bank1.Reg4 - Timer Low Byte Register (TMRL) ..................................................................46
7.1.13 Bank1.Reg5 - Timer High Byte Register (TMRH).................................................................47
8. PARALLEL PORT ........................................................................................................................ 47
8.1 Printer Interface Logic ........................................................................................................ 47
8.2 Enhanced Parallel Port (EPP)............................................................................................ 48
8.2.1 Data Swapper ......................................................................................................................49
8.2.2 Printer Status Buffer.............................................................................................................49
8.2.3 Printer Control Latch and Printer Control Swapper ..............................................................49
8.2.4 EPP Address Port ................................................................................................................50
8.2.5 EPP Data Port 0-3................................................................................................................51
8.2.6 Bit Map of Parallel Port and EPP Registers .........................................................................51
8.2.7 EPP Pin Descriptions ...........................................................................................................52
8.2.8 EPP Operation .....................................................................................................................52
8.3 Extended Capabilities Parallel (ECP) Port......................................................................... 53
8.3.1 ECP Register and Mode Definitions .....................................................................................53
8.3.2 Data and ecpAFifo Port ........................................................................................................54
8.3.3 Device Status Register (DSR)..............................................................................................54
8.3.4 Device Control Register (DCR) ............................................................................................55
8.3.5 cFifo (Parallel Port Data FIFO) Mode = 010.........................................................................56
8.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 ..............................................................................56
Publication Release Date: May 31, 2005
-3-
Revision A1
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