W83627SF Ver la hoja de datos (PDF) - Winbond
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W83627SF Datasheet PDF : 116 Pages
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W83627SF
8.3.7 tFifo (Test FIFO Mode) Mode = 110.....................................................................................56
8.3.8 cnfgA (Configuration Register A) Mode = 111......................................................................56
8.3.9 cnfgB (Configuration Register B) Mode = 111......................................................................56
8.3.10 ecr (Extended Control Register) Mode = all .........................................................................57
8.3.11 Bit Map of ECP Port Registers .............................................................................................58
8.3.12 ECP Pin Descriptions ...........................................................................................................59
8.3.13 ECP Operation .....................................................................................................................60
8.3.14 FIFO Operation ....................................................................................................................60
8.3.15 DMA Transfers .....................................................................................................................61
8.3.16 Programmed I/O (NON-DMA) Mode ....................................................................................61
8.4 Extension FDD Mode (EXTFDD) ....................................................................................... 61
8.5 Extension 2FDD Mode (EXT2FDD) ................................................................................... 61
9. KEYBOARD CONTROLLER ....................................................................................................... 62
9.1 Output Buffer ...................................................................................................................... 63
9.2 Input Buffer ......................................................................................................................... 63
9.3 Status Register................................................................................................................... 63
9.4 Commands ......................................................................................................................... 64
9.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC.................................... 66
9.5.1 KB Control Register (Logic Device 5, CR-F0) ......................................................................66
9.5.2 Port 92 Control Register (Default Value = 0x24) ..................................................................66
10. GENERAL PURPOSE I/O ........................................................................................................... 67
11. PLUG AND PLAY CONFIGURATION ......................................................................................... 69
11.1 Compatible PnP ................................................................................................................. 70
11.1.1 Extended Function Registers ...............................................................................................70
11.1.2 Extended Functions Enable Registers (EFERs)...................................................................71
11.1.3 Extended Function Index Registers (EFIRs), Extended Function Data Registers (EFDRs) .71
11.2 Configuration Sequence..................................................................................................... 71
11.2.1 Enter the extended function mode .......................................................................................71
11.2.2 Configurate the configuration registers.................................................................................71
11.2.3 Exit the extended function mode ..........................................................................................71
11.2.4 Software programming example...........................................................................................72
12. ACPI REGISTERS FEATURES................................................................................................... 73
13. SMART CARD INTERFACE........................................................................................................ 74
13.1 Receiver Buffer Register (RBR, read only at "base address + 0" when BDLAB = 0)....... 74
13.2 Transmitter Buffer Register (TBR, write only at "base address + 0" when BDLAB = 0)... 74
13.3 Interrupt Control Register (ICR, at "base address + 1" when BDLAB = 0)....................... 74
13.4 Interrupt Status Register (ISR, read only at "base address + 2") ..................................... 75
13.5 Smart Card FIFO Control Register (SCFR, write only at "base address + 2") ................. 76
13.6 Smart Card Control Register (SCCR, write only at "base address + 3") .......................... 77
13.7 Interrupt Enable Register (IER, at "base address + 4") .................................................... 77
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