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W89C982AF

INTEGRATED MULTIPLE REPEATER II

Winbond 

Preliminary W89C982AF

INTEGRATED MULTIPLE REPEATER II

GENERAL DESCRIPTION................................................................................................................. 2

FEATURES........................................................................................................................................ 2

ORDERING INFORMATION.............................................................................................................. 2

SYSTEM DIAGRAM .......................................................................................................................... 3

PIN CONFIGURATION ...................................................................................................................... 3

PIN DESCRIPTION ........................................................................................................................... 4

BLOCK DIAGRAM ............................................................................................................................. 8

FUNCTIONAL DESCRIPTION ........................................................................................................... 8

AUI Interface and Twisted Pair Line Transceiver ..........................................................................................8

Link Test Function.........................................................................................................................................8

Automatic Polarity Reversal Function ...........................................................................................................9

Port Partition/Reconnection Logic.................................................................................................................9

Port Status Direct Report Function ...............................................................................................................9

Initial State After Reset ...............................................................................................................................11

Management Logic and Management Interface .........................................................................................11

IMPR II Programmable Options..................................................................................................................15

The IMPR II Kernel Logic............................................................................................................................15

Inter-IMPR II Interface.................................................................................................................................16

ABSOLUTE MAXIMUM RATINGS ................................................................................................... 17

DC CHARACTERISTICS ................................................................................................................. 17

AC CHARACTERISTICS ................................................................................................................. 19

System Clock Timing..................................................................................................................................19

Reset Timing...............................................................................................................................................19

Management Bus Clock Timing..................................................................................................................20

Management Bus Carrier Sense Timing.....................................................................................................20

Inter-IMPR II Interface Input Timing ............................................................................................................21

Inter-IMPR II Interface Output Timing .........................................................................................................22

Inter-IMPR II Interface Collision Timing.......................................................................................................23

Inter-IMPR II Interface to AUI/TP Port Timing.............................................................................................23

Output Driver Timing...................................................................................................................................24

Repetition Timing (part 1) ...........................................................................................................................24

Repetition Timing (part 2) ...........................................................................................................................25

Link Test Timing..........................................................................................................................................26

PACKAGE DIMENSIONS ................................................................................................................ 28

Publication Release Date: November 1996

-1-

Revision A1

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