RTL8196C-GR Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8196C-GR Datasheet PDF : 44 Pages
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RTL8196C
Datasheet
Pin Name
Pin No.
Type Description
SDRAM Control
MCLK
84
O SDRAM Clock
MCLKE
40
O SDRAM Clock Enable
MCS0#
66
O SDRAM Bank 0 Chip Select
MCS1#
67
O SDRAM Bank 1 Chip Select
BS[1:0]
63, 65
O SDRAM Chip Bank Select [1:0]
Shared with A[14:13]
RAS#
69
O Raw Address Strobe for SDRAM
CAS#
70
O Column Address Strobe for SDRAM
WE#
71
O Write Enable for SDRAM
LDQM
UDQM
k NF_CS0#
lte NF_CS1#
OE#
a IAL WE#
e NT N SF_CS0#
R E IO SF_CS1#
ID AT SF_SDIO[3:0]
R SF_SCK
ONF ORPO UART_TX
C C UART_RX
TE JTAG_TCK
Z JTAG_TMS
for JTAG_TDO
72
85
41
40
69
71
41
40
43, 45, 46, 47
48
37
36
100
97
98
O Lower Data Mask Output to SDRAM
Corresponds to D[7:0]
Pin shared with A[15]
O Upper Data Mask Output to SDRAM
Corresponds to D[15:8]
Pin shared with A[16]
NOR Type Flash Control
O ROM Bank 0 Chip Select for NOR Type Flash Memory
O ROM Bank 0 Chip Select for NOR Type Flash Memory
O Output Enable (OE#) for NOR Type Flash.
Pin shared with SDRAM RAS#
O Write Enable for NOR Type Flash.
Pin shared with SDRAM WE#
SPI Serial Flash Control
O SPI Serial Flash Chip Select 0
Pin shared with NOF_CS0#
O SPI Serial Flash Chip Select 1
Pin shared with NOF_CS1#
I/O SPI Serial Flash Serial Data Input/Output
O SPI Serial Flash Serial Clock Output
The SF_SDI will be driven on the falling edge
The SF_SDO will be latched on the rising edge
UART
O UART Data Transmit Serial Output
IPD UART Data Receive Serial Input
JTAG
IPU JTAG Test Clock
IPU JTAG Test Mode Select
O JTAG Test Data Output
JTAG_TDI
99
IPU JTAG Test Data In
JTAG_TRST#
96
IPU JTAG Test Reset
LED
LED_PORT[4:0]
107, 105, 104, 102, 101 O Link/Activity Status of 5 Ethernet Ports
GPIO
GPIOA[7:0]
36, 98, 99, 97, 96, 100, I/O GPIO Port A
40, 67
IEEE 802.11n AP/Router Network Processor with EEE 7
Track ID: JATR-2265-11 Rev. 0.7
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