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M6MGB166S2BWG

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS 3.3V-ONLY FLASH MEMORY

MITSUBISHI ELECTRIC  

MITSUBISHI LSIs

M6MGB/T166S2BWG

16,777,216-BIT (1,048,576 -WORD BY 16-BIT ) CMOS

3.3V-ONLY FLASH MEMORY &

2,097,152-BIT (131,072-WORD BY 16-BIT) CMOS SRAM

Stacked-CSP (Chip Scale Package)

FUNCTION

The Flash Memory of M6MGB/T166S2BWG includes on-chip

program/erase control circuitry. The Write State Machine (WSM)

controls block erase and byte/page program operations.

Operational modes are selected by the commands written to the

Command User Interface (CUI). The Status Register indicates the

status of the WSM and when the WSM successfully completes the

desired program or block erase operation.

A Deep Powerdown mode is enabled when the F-RP# pin is at

GND, minimizing power consumption.

Read

The Flash Memory of M6MGB/T166S2BWG has three read

modes, which accesses to the memory array, the Device Identifier

and the Status Register. The appropriate read command are

required to be written to the CUI. Upon initial device powerup or

after exit from deep powerdown, the Flash Memory automatically

resets to read array mode. In the read array mode, low level input

to F-CE# and F-OE#, high level input to F-WE# and F-RP#, and

address signals to the address inputs (F-A19-F-A17,A16-A0)

output the data of the addressed location to the data input/output (

D15-D0).

Write

Writes to the CUI enables reading of memory array data, device

identifiers and reading and clearing of the Status Register. They

also enable block erase and program. The CUI is written by

bringing F-WE# to low level, while F-CE# is at low level and F-OE#

is at high level. Address and data are latched on the earlier rising

edge of F-WE# and F-CE#. Standard micro-processor write

timings are used.

Alternating Background Operation (BGO)

The Flash Memory of M6MGB/T166S2BWG allows to read array

from one bank while the other bank operates in software

command write cycling or the erasing / programming operation in

the background. Read array operation with the other bank in BGO

is performed by changing the bank address without any additional

command. When the bank address points the bank in software

command write cycling or the erasing / programming operation,

the data is read out from the status register. The access time with

BGO is the same as the normal read operation.

Output Disable

When F-OE# is at VIH, output from the devices is disabled. Data

input/output are in a high-impedance(High-Z) state.

Standby

When F-CE# is at VIH, the device is in the standby mode and

its power consumption is reduced. Data input/output are in a

high-impedance(High-Z) state. If the memory is deselected

during block erase or program, the internal control circuits

remain active and the device consume normal active power

until the operation completes.

Deep Power-Down

When F-RP# is at VIL, the device is in the deep powerdown

mode and its power consumption is substantially low. During

read modes, the memory is deselected and the data

input/output are in a high-impedance(High-Z) state. After

return from powerdown, the CUI is reset to Read Array , and

the Status Register is cleared to value 80H.

During block erase or program modes, F-RP# low will abort

either operation. Memory array data of the block being altered

become invalid.

Automatic Power-Down (APD)

The Automatic Power-Down minimizes the power

consumption during read mode. The device automatically

turns to this mode when any addresses or F-CE# isn't

changed more than 200ns after the last alternation. The

power consumption becomes the same as the stand-by

mode. While in this mode, the output data is latched and can

be read out. New data is read out correctly when addresses

are changed.

4

Nov 1999 , Rev.2.3

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