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MX25L12855E

128M-BIT [x 1/x 2/x 4] CMOS MXSMIO™ (SERIAL MULTI I/O) FLASH MEMORY

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MX25L12855E

(22) Release from Deep Power-down (RDP), Read Electronic Signature (RES)................................................... 27

(23) Read Electronic Manufacturer ID & Device ID (REMS), (REMS2), (REMS4), (REMS4D).............................. 27

Table 6. ID Definitions ............................................................................................................................................ 28

(24) Enter Secured OTP (ENSO)............................................................................................................................ 28

(25) Exit Secured OTP (EXSO)............................................................................................................................... 28

(26) Read Security Register (RDSCUR)................................................................................................................. 28

Security Register Definition..................................................................................................................................... 29

(27) Write Security Register (WRSCUR)................................................................................................................. 29

(28) GPIO Expander................................................................................................................................................ 30

(28-1) GPIO Function Enable (GPIOEN)................................................................................................................ 30

(28-2) GPIO Function Disable (GPIODIS)............................................................................................................... 30

(28-3) GPIO Register Read/Write (GPIORW)......................................................................................................... 30

(28-4) GPIO Register Reset (GPIORST)................................................................................................................ 30

(29) Write Protection Selection (WPSEL)................................................................................................................ 32

WPSEL Flow........................................................................................................................................................... 32

(30) Single Block Lock/Unlock Protection (SBLK/SBULK)...................................................................................... 33

Block Lock Flow...................................................................................................................................................... 33

Block Unlock Flow................................................................................................................................................... 34

(31) Read Block Lock Status (RDBLOCK).............................................................................................................. 35

(32) Gang Block Lock/Unlock (GBLK/GBULK)........................................................................................................ 35

(33) Clear SR Fail Flags (CLSR)............................................................................................................................. 35

(34) Output Driving Configure (ODC)...................................................................................................................... 35

(35) Enable SO to Output RY/BY# (ESRY)............................................................................................................. 36

(36) Disable SO to Output RY/BY# (DSRY)............................................................................................................ 36

(37) Enter CFI Mode (ENCFI)................................................................................................................................. 36

POWER-ON STATE.................................................................................................................................................... 37

ELECTRICAL SPECIFICATIONS.............................................................................................................................. 38

ABSOLUTE MAXIMUM RATINGS.......................................................................................................................... 38

Figure 2. Maximum Negative Overshoot Waveform................................................................................................ 38

CAPACITANCE TA = 25°C, f = 1.0 MHz.................................................................................................................. 38

Figure 3. Maximum Positive Overshoot Waveform................................................................................................. 38

Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL................................................................... 39

Figure 5. OUTPUT LOADING................................................................................................................................ 39

Table 7. DC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ........ 40

Table 8. AC CHARACTERISTICS (Temperature = -40°C to 85°C for Industrial grade, VCC = 2.7V ~ 3.6V) ....... 41

Timing Analysis......................................................................................................................................................... 43

Figure 6. Serial Input Timing................................................................................................................................... 43

Figure 7. Output Timing........................................................................................................................................... 43

Figure 8. Serial Input Timing for Double Transfer Rate Mode................................................................................. 44

Figure 9. Serial Output Timing for Double Transfer Rate Mode.............................................................................. 44

Figure 10. WP# Setup Timing and Hold Timing during WRSR when SRWD=1...................................................... 45

Figure 11. Write Enable (WREN) Sequence (Command 06).................................................................................. 45

Figure 12. Write Disable (WRDI) Sequence (Command 04)................................................................................... 45

P/N: PM1466

REV. 0.05, MAR. 05, 2009

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