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MX25L12855E

128M-BIT [x 1/x 2/x 4] CMOS MXSMIO™ (SERIAL MULTI I/O) FLASH MEMORY

Macronix International 

MX25L12855E

GENERAL DESCRIPTION

The MX25L12855E is 134,217,728 bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When

it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x 4. The MX25L12855E

features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus

signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device

is enabled by CS# input.

The MX25L12855E provides high performance read mode, which may latch address and data on both rising and

falling edge of clock. By using this high performance read mode, the data throughput may be doubling. Moreover,

the performance may reach direct code execution, the RAM size of the system may be reduced and further saving

system cost.

The MX25L12855E provides sequential read operation on whole chip and multi-I/O features.

When it is in dual I/O mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and

data output. When it is in quad I/O mode, the SI pin, SO pin, WP# pin and NC pin become SIO0 pin, SIO1 pin, SIO2

pin and SIO3 pin for address/dummy bits input and data Input/Output.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the

specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for Continuously Program mode, and erase command is executes on sector (4K-byte),

block (32K-byte/64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see Security Features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 100uA DC cur-

rent.

The MX25L12855E utilizes MXIC's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Additional Features

Additional Protection and Security

Read Performance

Features

Part

Name

Permanent

Lock and

read lock

Individual

block (or

sector)

protection

1 I/O Read 2 I/O Read

(104 MHz) (70 MHz)

4 I/O Read

(70 MHz)

1 I/O DT

Read

(50 MHz)

2 I/O DT

Read

(50 MHz)

MX25L12855E

V

V

V

V

V

V

V

4 I/O DT

Read

(50 MHz)

V

8 I/O

Parallel

Mode

(6 MHz)

V

Additional

Features

Part

Name

RES

(command: AB

hex)

MX25L12855E

88 (hex)

REMS

(command: 90

hex)

C2 88 (hex)

(if ADD=0)

Identifier

REMS2

(command: EF

hex)

C2 88 (hex)

(if ADD=0)

REMS4

(command: DF

hex)

C2 88 (hex)

(if ADD=0)

REMS4D

(command: CF

hex)

C2 88 (hex)

(if ADD=0)

RDID (command:

9F hex)

C2 26 18 (hex)

P/N: PM1466

REV. 0.05, MAR. 05, 2009

7

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