CB55000 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Lista de partido

CB55000

HCMOS7 Standard Cells

STMicroelectronics 

Table 4. Package / pin availability

Package Name

CB55000 Series

20 r

28 r

44 r

r

r

48

r

64

r

rr

68 r

80

r

r

84 r

100

r

r

120

rr r

128

rr r

144

r

rr r

160

rr r

176

r

208

rr r

7 DESIGN METHODOLOGY

STMicrolectronics (STM) ASIC design flow is intended for high performance, high complexity submicron ASIC

designs. 3rd parties tools from leading EDA vendors such as Synopsys, Cadence, Mentor Graphics and STM

proprietary systems are integrated into a framework free design environment that efficiently supports all design

phases.

A hierarchical design methodology with a FastLoop, between floorplanning timing-driven placement and syn-

thesis/static timing analysis, guarantees a fast timing prediction and closure after routing.

Other features such as hierarchical Clock tree synthesis, advanced test methodology, formal verification, 3D

parasitic extraction, Crosstalk analysis, IP-reuse, qualifies the STM ASIC design flow as one of the industry's

leading solutions for today's and tomorrow's complex designs.

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