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CB55000

HCMOS7 Standard Cells

STMicroelectronics 

CB55000 Series

HCMOS7 Standard Cells

FEATURE

s 0.25 micron drawn (0.20 micron effective

channel length process), six layers of metal

connected by fully stackable vias and contacts,

Shallow Trench Isolation, low resistance,

salicided active areas and gates. Deep UV

lithography.

s 2.5 V optimized transistor with 3.3 V I/O and

supply interface capability.

s Average gate density: 30 K/mm2, plus low

power consumption of 70 nanoWatt/Gate/MHz/

Stdload.

s Two input NAND delay of 90 pS (typical) with

fanout=2.

s Library available in commercial, industrial and

military temperature range with supply ranging

from 2.70 V down to 1.8 V for the core

according to EIA/JESD 8-5 specification.

Additional low voltage range down to 1.5 V for

very low voltage/low power applications

supported

s Broad I/O functionality including:

– Low Voltage CMOS.

– Low Voltage TTL, PECL, HSTL, SSTL,

LVDS, PCI.

s AGP 2X and 4X, USB to support 2.5 V and 3.3

V I/O interface according to EIA/JESD 8A

specification.

s Drive capability up to 8 mA per buffer with slew

rate control, current spike suppression

impedance matching, and process

compensation capability to reduce delay

variation.

s Designs easily portable from previous

generations of CB45000 through cell mapping

with an average factor 2 density increase, 1.7

speed increase and 2.5 power reduction at

respective nominal voltages.

s Generators to support Single Port, Dual port

and multiple Port RAM, and ROMs with BIST

options.

s Extensive embedded function library including

ST DSP and micro-cores, third-party IPs,

Synopsys and Mentor Inventra synthetic

libraries ideally suited for complete System On

Chip fast integration .

s 80 µm pitch linear and 50 µm staggered pad

February 2002

ROM

DSP

DPRAM

ST20

CB55000 Super Integration

Cost Effective Product

s Architecture partitioning

s Trouble-free integration

s Application-specific

Your Product is Unique

s User specified cell integration

s Design confidentiality

s IP fully re-usable

libraries.

s Fully independent power and ground

configuration for core and I/Os supported.

s I/O ring capability up to 1500 pads.

s Latch-up trigger current > +/- 500 mA. ESD

protection above 4 kV in H.B.M.

s Oscillators and PLLs for wide frequency

spectrum.

s Broad range of more than 600 SSI cells.

s Design for test features including IEEE 1149.1

JTAG Boundary Scan architecture.

s Synopsys, Cadence and Mentor based design

systems with interface from multiple

workstations.

s Broad range of packaging solutions, including

BGA, LBGA, TQFP, PQFP, PLCC up to 1000

pins with enhanced power dissipation options.

s 1.25 GigaHertzGigabit DLL technique.

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