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CB65000

HCMOS8D 0.18µm Standard Cells Family

STMicroelectronics 

CB65000 Series

HCMOS8D 0.18µm Standard Cells Family

FEATURE

s 0.18 micron drawn, six layers of metal connected

by fully stackable vias and contacts, Shallow

Trench Isolation, low resistance, salicided

active areas and gates. Deep UV lithography.

s 1.8 V optimized High Performance and Low

Leakage transistors with 3.3 V I/O and supply

interface capability.

s Average gate density: 85K/mm2, plus low power

consumption of 30nanoWatt/Gate/MHz/

Stdload.

s Two input NAND delay of 35ps with High

Performane transistor and 60ps with Low

Leakage transistor.

s Library available in commercial, industrial and

military temperature range. Power supply

ranging from 1.2V and 1.95V for Core

(according to JESD 8-7 specification) and

between 3.0V and 3.6V for I/Os (alligned with

JESD 8-A specification).

s Broad I/O functionality including:

s Low Voltage CMOS.

s Low Voltage TTL,HSTL, SSTL.

s AGP 2X and 4X, USB, PCI, LVDS I/O interfaces

are also available.

s Drive capability up to 8 mA per buffer with slew

rate control, current spike suppression

impedance matching, and process

compensation capability to reduce delay

variation.

s Designs easily portable from previous

generations of CB55000 with an average factor

2 density increase, 30% speed improvement

s and 2.5 power reduction at respective nominal

voltages.

s

s Generators to support Single Port, Dual port

and multiple Port RAM, and ROMs with BIST

options.

s Extensive embedded function library including

ST DSP and micro-cores, third-party IPs,

Synopsys and Mentor Inventra synthetic

libraries ideally suited for complete System On

Chip fast integration .

s Embedded DRAM Capability

March 2002

CB65000 Super Integration

Cost Effective Product

s Architecture partitioning

s Trouble-free integration

s Application-specific

Your Product is Unique

s User specified cell integration

s Design confidentiality

s IP fully re-usable

s 80 µm pitch linear and 50 µm staggered pad

libraries.

s Fully independent power and ground

configuration for core and I/Os supported.

s I/O ring capability up to 1500 pads.

s Latch-up trigger current > ± 500 mA. ESD

protection above 4 kV in H.B.M.

s Oscillators and PLLs for wide frequency

spectrum.

s Broad range of more than 600 SSI cells.

s Design for test features including IEEE 1149.1

JTAG Boundary Scan architecture.

s Synopsys, Cadence and Mentor based design

systems with interface from multiple

workstations.

s Broad range of packaging solutions, including

PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP,

PLCC up to 1000 pins with enhanced power

dissipation options.

s 1.25 GigaHertzGigabit DLL technique.

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