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CB65000

HCMOS8D 0.18µm Standard Cells Family

STMicroelectronics 

CB65000 SERIES

4 DESIGN METHODOLOGY

STMicrolectronics (STM) ASIC design flow is intended for high performance, high complexity submicron ASIC

designs. 3rd parties tools from leading EDA vendors such as Synopsys, Cadence, Mentor Graphics and STM

proprietary systems are integrated into a framework free design environment that efficiently supports all design

phases.

A hierarchical design methodology with a FastLoop, between floorplanning timing-driven placement and syn-

thesis/static timing analysis, guarantees a fast timing prediction and closure after routing.

Other features such as hierarchical Clock tree synthesis, advanced test methodology, formal verification, 3D

parasitic extraction, Crosstalk analysis, IP-reuse, qualifies the STM ASIC design flow as one of the industry's

leading solutions for today's and tomorrow's complex designs.

Figure 6.

Functional & Timing Specification

HDL Description & Checks

Behavioural Simulation

Preliminary RTL Floorplan

Synthesis / STA

Floorplan

Physical Synthesis

SCAN Ordering and Routing

Scan Insertion

Verification

STA

Gate Level Full Timing Simulation

Functional / Formal Verification

Clock Tree Synthesis

Routing - Optimization

ATPG

Parasitic Extraction

Final Verification

STA

Gate Level Full Timing Simulation

Functional / Formal Verification

DRC / LVS

Prototype Fabrication

IDDQ

Testing

Final Fault

Analysis

Test Vectors

&

Final Test Program

Generation

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