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CB65000

HCMOS8D 0.18µm Standard Cells Family

STMicroelectronics 

CB65000 SERIES

3.3 I/O Buffer Libraries

Two basic buffer libraries are offered with CB65000, one 80 µm pad in line pitch library and one 50 µm stag-

gered pad library to support pad limited designs.

Apart from standard ESD and latch-up protections present in each I/O, a proprietary clamp within each power

supply provides proper paths to all types of ESD discharges, efficiently protecting the I/Os. As a result, the buff-

ers withstand more than 4 kV ESD according to Mil 883C Human Body Model specification.

In order to limit switching noise and keep a fixed buffer delay, independent of process, supply voltage and tem-

perature, compensated active slew rate buffers can be selected, providing a fixed and stable dI/dt.

In order to interface with 3.3 V application (from 3.0 up to 3.6 V), a wide range of 3.3 V capable input/output

buffers (mixable with standard 1.8V ones) can be chosen. In this case the 3.3 V rail in the chip periphery must

be powered through a 3.3 V external supply.

True 5 volt tolerant input buffer is also available to allow different power level managment.

Dedicated I/Os for special applications have developed, like :

– UDMA for Hard Disk Interface

– LVDS and PECL for Telecom Standard

– PCI for PC Peripheral Interface

– USB for Universal Serial Interface

3.4 I/O Test Interface

The I/O cells have a dedicated test interface to facilitate parametric and lddq testing of devices. This test interface

connects standard core signals or dedicated test signals to the I/O cells allowing all output buffers to be driven high,

low or put into tri-state regardless of the state of the internal logic.

This greatly simplifies parametric testing of the device and also assisting customers who wish to use this feature

during board testing. Note that all output buffers can be tri-stated by this function including buffers that normally

do not tri-state.

This test function also turns off all pull down resistors, shuts down all differential receivers and converts them

into standard CMOS receivers. This allows lddq test methodologies to be employed in a very efficient way,

avoiding unneeded circuit overhead.

3.5 Macrocells

The CB65000 series has internal macrocells that are robust in variety and performance. The cell selection has

been driven by the need of Synthesis and HDL-based design techniques. This offering is rich in buffers, complex

combination cells and multi-power drive cells, which allow the Synthesis tool to create a netlist compatible with

the requirements of Place and Route tools.

Macrofunctions are a series of soft-macros facilitating quick capture of large functional blocks and are available

for such functions as counters, shift registers and adders. Macrofunctions are implemented at layout by utilizing

macrocells and interconnecting to create the logic function.

3.5.1 Module generators

A series of module generators using compiled cell generation techniques are available to support a range of

megacells. These modules enable the designer to choose individual parameters in order to create a compiled

cell, which meets the specific application requirements. These include ROM, single and dual port RAM, multi-

port RAM and FIFO, some of them specifically optimized for speed and for power. All memories have a complete

standby mode where current consumption is limited to process leakage.

High Density Memories are also available to fully exploiting the technology capability.

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