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MX98L715BEC

3.3V SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98L715BEC

5.2.5 INTERRUPT STATUS REGISTER ( CSR5 )

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WKUPI-Wake Up event Interrupt

LC-Link Change

EB-Error Bits

TS-Transmit Process State

RS-Receive Process State

NIS-Normal Interrupt Summary

AIS-Abnormal Interrupt Summary

ERI-Early Receive Interrupt

FBE-Fatal Bus Error

LF-Link Fail

GTE-General Purpose Timer Expired

ETI-Early Transmit Interrupt

RWT-Receive Watchdog Timeout

RPS-Receive Process Stopped

RU-Receive Buffer Unavailable

RI-Receive Interrupt

UNF-Transmit Underflow

LPANCI-Link Pass/Autonegotiation

Completed Interrupt

TJT-Transmit Jabber Timeout

TU-Transmit Buffer Unavailable

TPS-Transmit Process Stopped

TI-Transmit Interrupt

Field

28

27

25:23

22:20

19:17

16

15

14

13

12

Name

WKUPI

LC

EB

TS

RS

NIS

AIS

ERI

FBE

LF

Description

Wake Up event interrupt. Set if wake-up event occurs in power-down mode.

100 Base-TX link status has changed either from pass to fail or fail to pass.

Read CSR12<1> for 100 Base-TX link status.

Error Bits, read only, indicating the type of error that caused fatal bus error.

Transmit Process State, read only bits indicating the state of transmit process.

Receive Process State, read only bits indicating the state of receive process.

Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and

CSR5<28>.

Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>,

CSR5<7>, CSR5<8>, CSR5<9>, CAR5<10>, CSR5<11> and CSR5<13>, CSR5<27>.

Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes

has been received in chain mode.

Fatal Bus Error, indicating a system error occurred, MX98L715BEC will disable all bus

access.

Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when

CSR6<18>=0, CSR14<8>=1, and CSR13<3>=0.

P/N:PM0695

REV. 0.3, MAR. 30, 2001

19

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