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BT8110

High-Capacity ADPCM Processor

Conexant Systems 

Bt8110/8110B

High-Capacity ADPCM Processor

Appendix B . T1 Speech Compression

B.1 Introduction

the free-running synchronization signal TX SYNC A on the Bt8300 (this signal

must also be connected to TX SYNC B IN to synchronize the B side transmitter).

The Bt8110/8110B clock of 6.144 MHz is obtained by internally dividing and

gapping the 12.352 MHz input clock to the Bt8110/8110B.

The ADPCM inputs and outputs are timed by the signal ADPCM_STB. This

signal will be identical at both Bt8110/8110Bs. The input to each is applied to the

parallel input PSIG[7:0], with the most significant bit at PSIG[7]. The output is

obtained from the parallel signal output D[7:0], with the most significant bit at

D[7].

The input data must be valid at the positive edge of ADPCM_STB and the

output data is valid at the positive edge. Due to the processing delay of the

Bt8110/8110B, there is a five-channel offset between the timing of the ADPCM

input and PCM output.

The ADPCM output is always 5 bits or less (for 40 kbit/s coding and for all

embedded codes). The ADPCM input includes up to 5 ADPCM input bits and 2

bits to indicate the number of bits in the decoder input when embedded encoding

is used.

The MICREN input must be connected to the supply voltage to enable the

microprocessor interface. The PSIGEN pin must be held low. If the RESET input

is not used to reset the algorithm externally, it should be held low; otherwise it

should be generated. The RESET input is active high.

B.1.2 Functional Timing Diagram

The timing of the T1 speech compression interface circuit is given in Figure B-2.

The clock signal is 12.352 MHz and is applied to the Bt8300 and both

Bt8110/8110Bs.

The SYNC signal to the Bt8110/8110B is the multiframe synchronization

output of the Bt8300. This signal provides bit and channel synchronization to the

Bt8110/8110Bs. The SYNC signal has a period of 3 ms; the timing diagram

shows the beginning of the frame at the end of the 3 ms period.

The ADPCM_STB signal is an enable and clock output for the

Bt8110/8110Bs. Its positive edge occurs when the ADPCM input is clocked into

the circuit and the ADPCM output is available from the ROM data pins. The

frame-bit location can be identified from the wide interval on this signal, which

occurs once per frame.

The PCM serial input and output timing is determined by the Bt8300

synchronization. The two parts are designed so that as long as the clocks and

synchronization signals are provided as shown in Figure B-1, the serial interface

will operate properly. Each of the signals is clocked by the respective input

circuitry near the middle of the signaling interval, so the interconnection circuitry

is not critical. This makes it possible, for instance, to add drop-and-insert or other

processing functions at the PCM interface.

NOTE: The ADPCM inputs are taken from the parallel input PSIG[7:0] for the

Bt8110B, and PSIG[7:1] for the Bt8110. The outputs are available on the

ROM data output D[7:0] for the Bt8110B, and D[7:1] for the Bt8110. Note

that encoding is provided for the timeslots that normally carry framing and

signaling information.

100060C

Conexant

B-3

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