BT8110 Ver la hoja de datos (PDF) - Conexant Systems
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BT8110 Datasheet PDF : 84 Pages
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Appendix B . T1 Speech Compression
B.1 Introduction
Bt8110/8110B
High-Capacity ADPCM Processor
There is an offset in the timing between the input and the output signals
caused by the processing delay of the Bt8110/8110B. In Figure B-2, ADPCM-3 is
the encoded output from PCM-3 and ADPCM-22 results in the decoded PCM-22.
This offset must be accounted for in the processing for speech signals or can be
eliminated by delaying the encoded output by 19 channel counts.
If the RESET input pin is used to reset the ADPCM algorithm according to
ANSI Standard T1.303–1989 and ITU-T G.726, the timing is as shown in the
Figure B-2. Note that the RESET input has to be applied approximately 2 µs
before the corresponding ADPCM input; it is possible to use the PCM_STB
signal to latch reset inputs for the ADPCM signal stream and the ADPCM_STB
signal to latch reset inputs for the PCM input stream.
In 48-channel designs, it may be helpful to have a single interleaved parallel
bus. The signal PCM_STB, which is also an output from each Bt8110/8110B, can
be used to clock odd inputs and outputs on and off a single parallel bus.
Figure B-2. T1 Speech Compression Functional Timing Diagram
12.352
MHz CLOCK
6.176 MHz
INT. CLK
SYNC
ADPCM_STB
1.544 Mbit/s
SERIAL_IN
8
S
2
3
4
5
6
7
8
PCM-24
1.544 Mbit/s
SERIAL_OUT 8 S 2 3 4 5 6 7 8
PCM-24
F S23 4 5 67 8S2 34
PCM-1
PCM-2
S
2 3 4 5 6 7 8 S23 4
PCM-1
PCM-2
PSIG[7:0]
ADPCM-3
ADPCM-4
ADPCM-5
D[7:0]
ADPCM-22
PCM-1
ADPCM-23
PCM-2
ADPCM-24
PCM_STB
RESET
D[7:0] Int (1)
PCM-1
ADPCM-22
ADPCM-4
PCM-1
PCM-2
ADPCM-23
ADPCM-5
PCM-2
PCM-3
ADPCM-24
NOTE(S):
(1) Bt8110B only.
100060_022
B-4
Conexant
100060C
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