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T15M1024A

128K X 8 LOW POWER CMOS STATIC RAM

Taiwan Memory Technology 

tm TE

CH

WRITE CYCLE 1 ( WE Controlled)

tWC

Add ress

CE1

tA W

tCW

tWR

CE2

WE

DOUT

D IN

tA S

H ig h -Z

tWP

tWHZ

H ig h-Z

tDW

tOW

tDH

WRITE CYCLE 2 ( CE Controlled)

tWC

Add ress

CE1

CE2

WE

tAS

tAW

tCW

tWP

tWR

T15M1024A

DOUT

D IN

H ig h -Z

H ig h -Z

tDW

tDH

H ig h -Z

DO N'T CAR E

UN D E FIN E D

NOTES ( WRITE CYCLE ) :

1. A write occurs during the overlap of a low CE1 , a high CE2 and a low WE . A write begins at

the lateat transition among CE1 goes low, CE2 going high and WE going low. A write end at

the earliest transition among CE1 going high, CE2 going low and WE going high. tWP is

measured from the beginning of write to the end of write.

2. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change.

TM Technology Inc. reserves the right

P. 8

to change products or specifications without notice.

Publication Date: OCT. 2004

Revision:C

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