SMS44S Ver la hoja de datos (PDF) - Summit Microelectronics
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SMS44S Datasheet PDF : 16 Pages
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SMS44
Longdog timer will generally be programmed to be of
longer duration than the watchdog and it will generate a
reset if it times out. Both timers are cleared by a low to high
transition on WLDI and they both start simultaneously.
If the watchdog should timeout the device status will be
recorded in the status register. If the Longdog times out
RESET# will drive low either until a WLDI clear is received
or until tPRTO (whichever occurs first), at which time it will
return high. Refer to Figures 3 and 4 illustrating the action
of RESET# and IRQ# with respect to the Watchdog and
Longdog timers and the WLDI input.
When the Longdog times out, a reset will be generated.
When reset returns high (after tPRTO or after a WLDI
strobe) both timers are reset to time zero. Therefore, if the
Longdog tPLDTO is equal to or shorter than the watchdog
tPWDTO, the reset will effectively clear the interrupt before
it can drive the output low.
7
MSB
6
Address
Select
54
PUP#3
32
PUP# State
PUP#2
1
0
LSB
PUP#1
If WLDI is held low the timers will free-run generating a
series of interrupts and resets. If WLDI is held high the
interrupt (watchdog) output will be disabled and only the
reset (Longdog) output will be active.
Lock AS0 1 0 1 0 1 0
x
0
Device type address 1010, responds
only to biased A2 & A1 combinations
x
1
Device type address 1011, responds
only to biased A2 & A1 combinations
0 x Configuration read/write enabled
7
MSB
6
5
43
2
SEQ RTO1 RTO0 LD1 LD0 WD2
1
0
LSB
WD1 WD0
1 x Configuration read/write locked out
2047 Table06 1.0
Table 6. Configuration Register 7
x x x 00
x x x01
x x x 10
Longdog Off
1600ms
3200ms
Register 6 is also used to set the programmable reset
timeout period (tPRTO) and to select the sequence option.
x x x 11
6400ms
x 0 0xx
x
0
1xx
x
1 0 xx
x
1
1xx
0 x x xx
tPRTO = 25ms
tPRTO = 50ms
tPRTO = 100ms
tPRTO = 200ms
Sequence On
1x x xx
Sequence Off
2047 Table04 1.0
Table 4. Configuration Register 6
7
MSB
6
5
SEQ RTO1 RTO0
43
LD1 LD0
OFF
400ms
800ms
1600ms
2
WD2
0
0
1
1
1
0
LSB
WD1 WD0
00
11
00
0
1
Bit 1
0
0
1
1
Bit 0
0
tPDLYX
0ms (no) Delay
1
25ms Delay
0
50ms Delay
1
100ms Delay
Table 7. PUP Delays
2047 Table07 1.0
Sequence Delay Programming
The sequence delays are programmed in register 7. Bit 7
of register 6, must be set to a “0” in order to enable the
sequencing of the PUP# outputs. Sequencing will not
commence until V0 is above its programmed threshold.
Each PUP# (-3, -2 and -1) is delayed according to the
states of its Bit 1 and Bit 0 as indicated in Table 7.
Refer to Figures 5 and 6 for the detailed timing relationship
of the programmable power-on sequencing.
3200ms
1 10
6400ms
111
2047 Table05 1.0
Table 5. Configuration Register 6
2047 2.3 10/23/00
8
SUMMIT MICROELECTRONICS, Inc.
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