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Q67100-H6440

ICs for Communications

Siemens AG 

SAB 82538

SAF 82538

Pin Definitions and Function (cont’d)

Pin No. Symbol

98

INTA

Input (I)

Function

Output (O)

I

Interrupt Acknowledge

If the interrupt is acknowledged via pin INTA, an

interrupt vector is output on D0…D7. All interrupt

sources are organized in groups with fixed

priority. The priority of the channels within a group

is fixed or adjusted dynamically (rotating priority

scheme, version 2 upward) (refer to chapter 2).

The generated interrupt vector refers to the

interrupt group and the requesting channel with

currently highest priority (although more than one

interrupt source/group may be active). Reaction

on INTA signal depends on the bus interface

mode and the cascading mode in conjunction with

the Interrupt Enable pins IE0-2 (ref. to IPC

register):

Motorola bus mode:

INT is reset with the rising edge of the following

valid INTA cycle if no further interrupt is pending.

The interrupt vector is output with signal DS.

Siemens/Intel bus mode:

INT is reset with the rising edge of the second

valid INTA cycle (2-cycle ’86 mode) if no further

interrupt is pending.

Slave mode:

Interrupt acknowledge is accepted if an interrupt

signal has been generated and the slave address

provided via IE0-2 corresponds to the

programmed value (IPC register).

Daisy Chaining mode:

Interrupt acknowledge is accepted if an interrupt

signal has been generated and Interrupt Enable

input IE1 is active during the following INTA cycle.

Note: Pins CS, DACKx have to be inactive

during an INTA cycle. If pin INTA is

not used, it has to be tied to VDD.

Semiconductor Group

15

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