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Q67100-H6440

ICs for Communications

Siemens AG 

SAB 82538

SAF 82538

Pin Definitions and Function (cont’d)

Pin No. Symbol

Input (I)

Function

Output (O)

1

DRT0

O

2

DRT1

3

DRT2

4

DRT3

5

DRT4

6

DRT5

7

DRT6

8

DRT7

DMA Request Transmitter (Channel 0 ... 7)

The transmitter on a serial channel requests a

DMA transfer by activating the corresponding

DRT line. The request remains active as long as

the corresponding Transmit FIFO requires data

transfers.

The amount of data bytes to be transferred from

the system memory to the ESCC8 serial channel

(= byte count) must be written first to the XBCH,

XBCL registers.

Always blocks of data (n x 32 bytes + REST,

n = 0, 1,…) are transferred till the Byte Count is

reached.

DRTn is deactivated with the beginning of the last

write cycle.

160

DRR0

O

159

DRR1

158

DRR2

157

DRR3

156

DRR4

155

DRR5

154

DRR6

153

DRR7

DMA Request Receiver (Channel 0 … 7)

The receiver on a serial channel requests a DMA

transfer by activating the corresponding DRT line.

The request remains active as long as the

corresponding Receive FIFO requires data

transfers, thus always blocks of data are

transferred.

DRRn is deactivated immediately following the

falling edge of the last read cycle.

Semiconductor Group

17

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