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DAP011

PWM Current−Mode Controller for High−Power Universal Off−Line Supplies

ON Semiconductor 

DAP011/DAP011C

As soon as VCC reaches VCCON, drive pulses are delivered

on Pin 9 and the auxiliary winding increases the voltage on

the VCC pin. Because the output voltage is below the target

(the SMPS is starting up), the controller smoothly ramps−up

the peak current to Imax (1.0 V / Rsense) which is reached

after a typical soft−start period. This soft−start period lasts

typically 10% of what has been selected for the fault timer

via Pin 3. As soon as the peak current setpoint reaches its

maximum (during the startup period but also anytime an

overload occurs), an internal error flag is asserted, Ip flag,

indicating that the system has reached its maximum current

limit set point (Ip = Ip maximum). As soon as the error flag

gets asserted, the current source on Pin 3 is activated and

charges up the capacitor connected to this pin. If the error

flag is still asserted when the timer capacitor has reached the

threshold level Vtim Fault, (which is about 100 ms with a

0.22 mF typically), then the controller assumes that the

power supply has really undergone a fault condition and

immediately stops all pulses to enter a safe burst operation.

Figure 22 depicts the VCC evolution during a proper startup

sequence, showing the state of the error flag:

Figure 22. An Error Flag Gets Asserted as soon as the Current Setpoint Reaches its Upper limit (1.0 V/Rsense)

Here the Timer Lasts 100 ms, a 0.22 mF Capacitor being Connected to Pin 3

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