6.12 Register 20 PHY 1_1 Register
Address
20:<15:0>
Name
PHY1_1
Description/Usage
PHY 1 register (functions as RTL8139C<78>)
6.13 Register 21 PHY 1_2 Register
Address
21:<15:0>
Name
PHY1_2
Description/Usage
PHY 1 register (functions as RTL8139C<78>)
6.14 Register 22 PHY 2 Register
Address
22<15:8>
22:<7:0>
Name
PHY2_76
PHY2_80
Description/Usage
PHY2 register for cable length test (functions as
RTL8139C<76>)
PHY2 register for PLL select (functions as
RTL8139C<80>)
6.15 Register 23 Twister_1 Register
Address
23:<15:0>
Name
TW_1
Description/Usage
Twister register (functions as RTL8139C<7c>)
6.16 Register 24 Twister_2 Register
Address
24:<15:0>
Name
TW_2
Description/Usage
Twister register (functions as RTL8139C<7c>)
6.17 Register 25 Test Register
Address
25<15:14>
25<13>
25:<12:8>
25<7:2>
25<1>
25<0>
Name
Test
Reserved
PHYAD[4:0]
Test
LINK10
LINK100
Description/Usage
Reserved for internal testing
Reflects the PHY address defined by external PHY
address configuration pins
Reserved for internal testing
1: Link established in 10Base OK
0: No link established in 10Base
1: Link established in 100Base OK
0: No link established in 100Base
RTL8201BL
Default/Attribute
R/W
Default/Attribute
R/W
Default/Attribute
RO
R/W
Default/Attribute
R/W
Default/Attribute
R/W
Default/ Attribute
R/W
RO
RO
RO
RO
2002-03-29
13
Rev.1.2