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78Q2120C

10/100BASE-TX Transceiver

TDK Corporation 

78Q2120C

10/100BASE-TX Transceiver

re-time the data signal and for conversion of the data to

NRZ format.

In 10BASE-T mode, the 10MHz receive clock is

recovered digitally from the Manchester data using a

DLL locked to the reference clock. When

Manchester-coded preambles are detected, the DLL

immediately re-aligns the phase of the clock to

synchronize with the incoming data. Hence clock

acquisition is fast and immediate.

100BASE-TX OPERATION

100BASE-TX Transmit

The 78Q2120C contains all of the necessary

circuitry to convert the transmit MII signaling from a

MAC to an IEEE-802.3 compliant data-stream

driving Cat-5 UTP cabling. The internal PCS

interface maps 4 bit nibbles from the MII to 5 bit

code groups as defined in table 24-1 of IEEE-802.3.

These 5 bit code groups are then scrambled and

converted to a serial stream before being sent to the

MLT-3 pulse shaping circuitry and line driver. The

pulse-shaper uses current modulation to produce

the desired output waveform. Controlled rise/fall

time in MLT-3 signal is achieved using an accurately

controlled voltage ramp generator. The line driver

requires an external 1:1 isolation transformer to

interface with the line media. The center-tap of the

primary side of the transformer should be connected

to the Vcc supply.

100BASE-TX Receive

The 78Q2120C receives a 125MBaud MLT-3 signal

through a 1:1 transformer. The signal then goes

through a combination of adaptive offset adjustment

(baseline wander correction) and adaptive

equalization. The effect of these circuits is to sense

the amount of dispersion and attenuation caused by

the cable and transformer, and restore the received

pulses to logic levels. The amount of gain and

equalization applied to the pulses varies with the

detected attenuation and dispersion and, therefore,

with the length of the cable. The 78Q2120C can

compensate for cable loss of up to 10dB at 16 MHz.

This loss is represented as test-chan 5 in Annex A of

the ANSI X3.263:199X specification. The equalized

MLT-3 data signal is bi-directionally sliced and the

resulting NRZI bit-stream is presented to the CDR

where it is re-timed and decoded to NRZ format.

The re-timed serial data is converted to parallel, then

descrambled and aligned into 5 bit code groups.

The receive PCS interface maps these code groups

to 4 bit data for the MII as outlined in Table 24-1 in

Clause 24 of IEEE-802.3.

PCS Bypass Mode (Auto-negotiate must be off)

The PCS Bypass mode is entered by pulling PCSBP

high or by setting register bit MR 16.1. In this mode

the 78Q2120C accepts scrambled 5 bit code words

into the pins TX_ER and TXD[3:0], TX_ER being the

MSB of the data input. The 5 bit code groups are

converted to MLT-3 signal for transmission.

The received MLT-3 signal is converted to 5 bit NRZ

code groups and output from the RX_ER and

RXD[3:0] pins, RX_ER being the MSB of the data

output. The RX_DV and TX_EN pins are unused in

PCS Bypass mode.

10BASE-T OPERATION

10BASE-T Transmit

The 78Q2120C takes 4 bit parallel NRZ data via the

MII interface and passes it through a parallel to

serial converter. The data is then passed through a

Manchester encoder, pre-emphasis pulse-shaper,

media filter, and finally to the twisted-pair line driver.

The pulse-shaper and filter ensures the output

waveforms meet the output voltage template and

spectral content requirements detailed in Clause 14

of IEEE-802.3. Interface to the twisted-pair media is

through two external 50Ω resistors and a center-

tapped 1:1 transformer. No external filtering is

required. During auto-negotiation and 10BASE-T

idle periods, link pulses are transmitted.

The 78Q2120C employs an onboard timer to

prevent the MAC from capturing a network through

excessively long transmissions. When this timer

expires, the chip enters the jabber state and

transmission is halted. The jabber state is exited

after the MII goes idle for 500±250ms.

10BASE-T Receive

The 78Q2120C receives Manchester-encoded

10BASE-T data through the twisted pair inputs and

re-establishes logic levels through a slicer with a

smart squelch function. The slicer automatically

adjusts its level after valid data with the appropriate

levels are detected. Data is passed on to the CRU

where the clock is recovered, and the data is re-

timed and decoded. From there, data enters the

serial-to-parallel converter for transmission to the

MAC via the Media Independent Interface. Interface

to the twisted-pair media is through an external

100Ω shunt resistor and a 1:1 transformer. Polarity

information is detected and corrected within internal

circuitry.

© 2003 TDK Semiconductor Corporation, Proprietary and Confidential

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Rev_1.1

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