78Q2120C Ver la hoja de datos (PDF) - TDK Corporation

Número de pieza

componentes Descripción

Lista de partido

78Q2120C

10/100BASE-TX Transceiver

TDK Corporation 

78Q2120C

10/100BASE-TX Transceiver

MII (continued)

NAME

PIN

RX_ER

25

MDC

18

MDIO

17

TYPE DESCRIPTION

COZ RECEIVE ERROR: RX_ER is asserted high when an error is detected during

frame reception. In PCS bypass mode, this pin becomes the MSB of the receive

5-bit code group. This pin is tristated in isolate mode.

CIS MANAGEMENT DATA CLOCK: MDC is the clock used for transferring data

via the MDIO pin.

CIO MANAGEMENT DATA INPUT/OUTPUT: MDIO is a bi-directional port used to

access management registers within the 78Q2120C. This pin requires an

external pull-up resistor as specified in IEEE-802.3.

PHY ADDRESS

NAME

PIN

PHYAD[4:0] 12-16

TYPE

CI

DESCRIPTION

PHY ADDRESS: Allows 31 configurable PHY addresses. The 78Q2120C

always responds to data transactions via the MII interface when the PHYAD

bits are all zero independent of the logic levels of the PHYAD pins.

PMA (PHYSICAL MEDIA ATTACHMENT) INTERFACE

NAME

PCSBP

PIN TYPE DESCRIPTION

64

CID PCS BYPASS: When high, the 100BASE-TX PCS is bypassed, as well as

the scrambler and descrambler functions. Scrambled 5-bit code groups for

transmission are applied to the TX_ER, TXD[3:0] pins and received on the

RX_ER, RXD[3:0] pins. The RX_DV and TX_EN signals are not valid in this

mode. PCS bypass mode is only valid when 100BASE-TX is enabled and

auto-negotiate disabled. This mode can also be entered with MR16.1.

CONTROL AND STATUS

NAME

RST

PWRDN

PIN TYPE DESCRIPTION

6

CIU ACTIVE-LOW RESET: When pulled low, the pin resets the chip. The reset

pulse must be long enough to guarantee stabilization of the supply voltage

and startup of the oscillator. There are 2 other ways to reset the chip:

i)

through the internal power-on-reset (activated when the chip is

being powered up)

ii)

through the MII register bit (MR0.15)

7

CID POWER-DOWN: The 78Q2120C may be placed in a low power consumption

state by setting this signal to logic high. While in power-down state, the

78Q2120C still responds to management transactions. The same power-

down state can also be activated through the PWRDN bit in the MII register

(MR0.11).

© 2003 TDK Semiconductor Corporation, Proprietary and Confidential

-7-

Rev_1.1

Share Link: