LF4415 Ver la hoja de datos (PDF) - LUXPIA

Número de pieza

componentes Descripción

Lista de partido

LF4415

Video Memory / FIFO

LUXPIA 

Power

PRELIMINARY

LF4460

LF4430

LF4415

Video Memory / FIFO

Detailed Signal Definitions

FRAME

MEMORY

VCCINT - Internal Core Power Supply (+1.8V, +2.5V or +3.3V)

VCCint is auto-regulated to an internal core VCC. All VCCint pins must be connected.

VCCO - Output Driver Power Supply (+1.8V, +2.5V or +3.3V)

VCCo is auto-regulated to an internal I/O driver VCC.. All VCCo power pins must be connected.

Clocks

WCLK0 - Write Clock 0

Data present on D0/D1 is latched and write pointer(s) are incremented on the rising edge of WCLK0 when

WEN0 is LOW. In dual-channel modes (MODE=x1xx), WCLK0 services input port D0 only.

WCLK1 - Write Clock 1

In dual-channel modes (MODE=x1xx), data present on D1[11-0] is latched on the rising edge of WCLK1

when WEN1 is LOW. In single-channel modes (MODE=x0xx), WCLK1 is ignored and can be tied LOW

unless used as an ‘ADDR’ external address bit (See ADDR descr.).

RCLK - Read Clock

Data is read from memory, read pointer(s) are incremented, and data is presented on its respective output

port (Qx[11-0]) on a rising edge of RCLK when RENx and OEx is LOW.

Data Input

Ports

I2C

Interface

D0[11-0] / D1[11-0] - Data Input Ports 0 / 1

D0/D1 is a 24-bit registered data input port. Please refer to Figure 5/6/7 on page 5/6/7 respectively.

For any single-channel configuration, including data widths of 16bits and higher, a combined D0/D1 input

port is enabled, with data latched on the rising edge of WCLK0. For data widths of 12bits or less,

use D0[11-0]. For two independent FIFOs, D0 services channel 0 and D1 services channel 1. In dual-

channel modes (MODE=x1xx), D1[11-0] is the 12-bit registered data input port for Channel 1. In this case

D0 is is latched on the rising edge of WCLK0 and D1[11-0] is latched on the rising edge of WCLK1. Bit 11

is the MSB in all modes. Any unused data input pins should be tied LOW.

SDA - Serial Data I/O

SDA is the standard bidirectional data pin of a two-wire serial microprocessor interface. External pullup

is required on both SDA and SCL pins.

SCL - Serial Clock Input

SCL is a standard two-wire serial microprocessor interface clock pin. Since this part cannot be the master

on a two-wire serial microprocessor interface, SCL functions as a dedicated input.

Address Port

ADDR23-0 - External Read/Write Address Port

ADDR is a 24-bit input port for real-time Write or Read address override (single channel mode). The

ADDR23-0 port shares input pins unused in single-channel mode. See Table 1 below. This address can

be mapped as a linear 24bit address (default) or as a 2-D address with row/column components. For 2-D

addresses ADDR11-0 defines the X/Column-coordinate and ADDR23-12 specifies the Y/Row-coordinate.

For 2-D addressing, see the description of ROW_LENGTH. ADDR defines the write address if RDWR=0

(ADDR is latched by a WCLK0 rising edge). ADDR defines the read address if RDWR=1 (ADDR is latched

by a WCLK0 rising edge). See Registers 0 and 1.

Table 1 - External Address ADDR[23:0] Mapping

Linear 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pins WIEN1 WEN1 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 REN1 COLLID1 PE1 PF1 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 WCLR1 WSET1 WCLK1

11 10 9 8

2-D

7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2

Y / Row Address

X / Column Address

10

LOGIC Devices Incorporated

www.logicdevices.com

10

High Performance Memory Product

January 23, 2008 LDS-44xx-A

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